commit ee67dcb837b37a1e1b538dec78ca9fd7c9f2315a
author Simon Dardis <simon.dardis@mips.com> Fri Jun 01 10:07:10 2018 +0000
committer Simon Dardis <simon.dardis@mips.com> Fri Jun 01 10:07:10 2018 +0000
tree 32cba417132395954cdd6b6f7f71065a24707923
parent 82ebdd792927f8658ed90e4e04245af5566c8138

[mips] Select the correct instruction for computing frameindexes

Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D47582

llvm-svn: 333736

llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp

diff --git a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
index 301a6c7..43469c2 100644
--- a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
+++ b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
@@ -200,6 +200,8 @@
      OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
     {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
      ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
+    {RT_OneInstr, OpCodes(Mips::LEA_ADDiu_MM, Mips::ADDIUR1SP_MM),
+     ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
     {RT_OneInstr, OpCodes(Mips::LHu, Mips::LHU16_MM), ReduceLXUtoLXU16,
      OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
     {RT_OneInstr, OpCodes(Mips::LHu_MM, Mips::LHU16_MM), ReduceLXUtoLXU16,