[SystemZ] Be more careful about inverting CC masks (conditional loads)
Extend r187495 to conditional loads. I split this out because the
easiest way seemed to be to force a particular operand order in
SystemZISelDAGToDAG.cpp.
llvm-svn: 187496
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index b7e966f..d9794b1 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -1012,6 +1012,27 @@
}
}
break;
+
+ case SystemZISD::SELECT_CCMASK: {
+ SDValue Op0 = Node->getOperand(0);
+ SDValue Op1 = Node->getOperand(1);
+ // Prefer to put any load first, so that it can be matched as a
+ // conditional load.
+ if (Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) {
+ SDValue CCValid = Node->getOperand(2);
+ SDValue CCMask = Node->getOperand(3);
+ uint64_t ConstCCValid =
+ cast<ConstantSDNode>(CCValid.getNode())->getZExtValue();
+ uint64_t ConstCCMask =
+ cast<ConstantSDNode>(CCMask.getNode())->getZExtValue();
+ // Invert the condition.
+ CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask,
+ CCMask.getValueType());
+ SDValue Op4 = Node->getOperand(4);
+ Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);
+ }
+ break;
+ }
}
// Select the default instruction
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index c0bb7b7..915891d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -735,10 +735,14 @@
}
class CondUnaryRSY<string mnemonic, bits<16> opcode,
- RegisterOperand cls, bits<5> bytes,
- AddressingMode mode = bdaddr20only>
- : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, cond4:$R3),
- mnemonic#"$R3\t$R1, $BD2", []>,
+ SDPatternOperator operator, RegisterOperand cls,
+ bits<5> bytes, AddressingMode mode = bdaddr20only>
+ : InstRSY<opcode, (outs cls:$R1),
+ (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
+ mnemonic#"$R3\t$R1, $BD2",
+ [(set cls:$R1,
+ (z_select_ccmask (load bdaddr20only:$BD2), cls:$R1src,
+ cond4:$valid, cond4:$R3))]>,
Requires<[FeatureLoadStoreOnCond]> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index a6efd41..341eb90 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -272,15 +272,13 @@
// Load on condition.
let isCodeGenOnly = 1, Uses = [CC] in {
- def LOC : CondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
- def LOCG : CondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
+ def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>;
+ def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
}
let Uses = [CC] in {
def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
}
-defm : CondLoad<LOC, GR32, nonvolatile_load>;
-defm : CondLoad<LOCG, GR64, nonvolatile_load>;
// Register stores.
let SimpleBDXStore = 1 in {
diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td
index 696ec4f..9d79439 100644
--- a/llvm/lib/Target/SystemZ/SystemZOperands.td
+++ b/llvm/lib/Target/SystemZ/SystemZOperands.td
@@ -111,15 +111,6 @@
!cast<Immediate>("imm"##bitsize))>;
//===----------------------------------------------------------------------===//
-// Manipulating CC masks
-//===----------------------------------------------------------------------===//
-
-def INVCC : SDNodeXForm<imm, [{
- unsigned Value = N->getZExtValue() ^ SystemZ::CCMASK_ANY;
- return CurDAG->getTargetConstant(Value, MVT::i8);
-}]>;
-
-//===----------------------------------------------------------------------===//
// Extracting immediate operands from nodes
// These all create MVT::i64 nodes to ensure the value is not sign-extended
// when converted from an SDNode to a MachineOperand later on.
diff --git a/llvm/lib/Target/SystemZ/SystemZPatterns.td b/llvm/lib/Target/SystemZ/SystemZPatterns.td
index 5419c2b..74cc5f0 100644
--- a/llvm/lib/Target/SystemZ/SystemZPatterns.td
+++ b/llvm/lib/Target/SystemZ/SystemZPatterns.td
@@ -54,20 +54,6 @@
def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
}
-// Record that INSN conditionally performs load operation LOAD into a
-// register of class CLS. The load may trap even if the condition is false.
-multiclass CondLoad<Instruction insn, RegisterOperand cls,
- SDPatternOperator load> {
- def : Pat<(z_select_ccmask (load bdaddr20only:$addr), cls:$new, uimm8zx4,
- uimm8zx4:$cc),
- (insn cls:$new, bdaddr20only:$addr, uimm8zx4:$cc)>,
- Requires<[FeatureLoadStoreOnCond]>;
- def : Pat<(z_select_ccmask cls:$new, (load bdaddr20only:$addr), uimm8zx4,
- uimm8zx4:$cc),
- (insn cls:$new, bdaddr20only:$addr, (INVCC uimm8zx4:$cc))>,
- Requires<[FeatureLoadStoreOnCond]>;
-}
-
// Record that INSN performs insertion TYPE into a register of class CLS.
// The inserted operand is loaded using LOAD from an address of mode MODE.
multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,