[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
The benchmarking summarized in
http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed
this is beneficial for a wide range of cores.
As is to be expected, quite a few small adaptations are needed to the
regressions tests, as the difference in scheduling results in:
- Quite a few small instruction schedule differences.
- A few changes in register allocation decisions caused by different
instruction schedules.
- A few changes in IfConversion decisions, due to a difference in
instruction schedule and/or the estimated cost of a branch mispredict.
llvm-svn: 306514
diff --git a/llvm/test/CodeGen/ARM/swifterror.ll b/llvm/test/CodeGen/ARM/swifterror.ll
index 3fd57c5..b02adf7 100644
--- a/llvm/test/CodeGen/ARM/swifterror.ll
+++ b/llvm/test/CodeGen/ARM/swifterror.ll
@@ -420,10 +420,10 @@
; CHECK-ARMV7-DAG: str r8, [s[[STK1:.*]]]
; CHECK-ARMV7-DAG: str r10, [s[[STK2:.*]]]
; Store arguments.
-; CHECK-ARMV7: mov r6, r3
-; CHECK-ARMV7: mov r4, r2
-; CHECK-ARMV7: mov r11, r1
-; CHECK-ARMV7: mov r5, r0
+; CHECK-ARMV7-DAG: mov r6, r3
+; CHECK-ARMV7-DAG: mov r4, r2
+; CHECK-ARMV7-DAG: mov r11, r1
+; CHECK-ARMV7-DAG: mov r5, r0
; Setup call.
; CHECK-ARMV7: mov r0, #1
; CHECK-ARMV7: mov r1, #2
@@ -435,10 +435,10 @@
; Restore original arguments.
; CHECK-ARMV7-DAG: ldr r10, [s[[STK2]]]
; CHECK-ARMV7-DAG: ldr r8, [s[[STK1]]]
-; CHECK-ARMV7: mov r0, r5
-; CHECK-ARMV7: mov r1, r11
-; CHECK-ARMV7: mov r2, r4
-; CHECK-ARMV7: mov r3, r6
+; CHECK-ARMV7-DAG: mov r0, r5
+; CHECK-ARMV7-DAG: mov r1, r11
+; CHECK-ARMV7-DAG: mov r2, r4
+; CHECK-ARMV7-DAG: mov r3, r6
; CHECK-ARMV7: bl _params_in_reg2
; CHECK-ARMV7: pop {r4, r5, r6, r7, r10, r11, pc}
define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
@@ -469,25 +469,25 @@
; CHECK-ARMV7: mov r8, #0
; CHECK-ARMV7: bl _params_in_reg2
; Restore original arguments.
-; CHECK-ARMV7: ldr r3, [s[[STK2]]]
-; CHECK-ARMV7: ldr r10, [s[[STK1]]]
+; CHECK-ARMV7-DAG: ldr r3, [s[[STK2]]]
+; CHECK-ARMV7-DAG: ldr r10, [s[[STK1]]]
; Store %error_ptr_ref;
-; CHECK-ARMV7: str r8, [s[[STK3:.*]]]
+; CHECK-ARMV7-DAG: str r8, [s[[STK3:.*]]]
; Restore original arguments.
-; CHECK-ARMV7: mov r0, r5
-; CHECK-ARMV7: mov r1, r11
-; CHECK-ARMV7: mov r2, r4
-; CHECK-ARMV7: mov r8, r6
+; CHECK-ARMV7-DAG: mov r0, r5
+; CHECK-ARMV7-DAG: mov r1, r11
+; CHECK-ARMV7-DAG: mov r2, r4
+; CHECK-ARMV7-DAG: mov r8, r6
; CHECK-ARMV7: bl _params_and_return_in_reg2
; Store swifterror return %err;
-; CHECK-ARMV7: str r8, [s[[STK1]]]
+; CHECK-ARMV7-DAG: str r8, [s[[STK1]]]
; Load swifterror value %error_ptr_ref.
-; CHECK-ARMV7: ldr r8, [s[[STK3]]]
+; CHECK-ARMV7-DAG: ldr r8, [s[[STK3]]]
; Save return values.
-; CHECK-ARMV7: mov r4, r0
-; CHECK-ARMV7: mov r5, r1
-; CHECK-ARMV7: mov r6, r2
-; CHECK-ARMV7: mov r11, r3
+; CHECK-ARMV7-DAG: mov r4, r0
+; CHECK-ARMV7-DAG: mov r5, r1
+; CHECK-ARMV7-DAG: mov r6, r2
+; CHECK-ARMV7-DAG: mov r11, r3
; Setup call.
; CHECK-ARMV7: mov r0, #1
; CHECK-ARMV7: mov r1, #2
@@ -496,12 +496,12 @@
; CHECK-ARMV7: mov r10, #0
; CHECK-ARMV7: bl _params_in_reg2
; Load swifterror %err;
-; CHECK-ARMV7: ldr r8, [s[[STK1]]]
+; CHECK-ARMV7-DAG: ldr r8, [s[[STK1]]]
; Restore return values for returning.
-; CHECK-ARMV7: mov r0, r4
-; CHECK-ARMV7: mov r1, r5
-; CHECK-ARMV7: mov r2, r6
-; CHECK-ARMV7: mov r3, r11
+; CHECK-ARMV7-DAG: mov r0, r4
+; CHECK-ARMV7-DAG: mov r1, r5
+; CHECK-ARMV7-DAG: mov r2, r6
+; CHECK-ARMV7-DAG: mov r3, r11
; CHECK-ARMV7: pop {r4, r5, r6, r7, r10, r11, pc}
define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
%error_ptr_ref = alloca swifterror %swift_error*, align 8