[Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFC
llvm-svn: 277220
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 5bbda9b..9802f7c 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -126,7 +126,7 @@
}
-static MachineBasicBlock::iterator moveInstrOut(MachineInstr *MI,
+static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI,
MachineBasicBlock::iterator BundleIt, bool Before) {
MachineBasicBlock::instr_iterator InsertPt;
if (Before)
@@ -134,20 +134,20 @@
else
InsertPt = std::next(BundleIt).getInstrIterator();
- MachineBasicBlock &B = *MI->getParent();
+ MachineBasicBlock &B = *MI.getParent();
// The instruction should at least be bundled with the preceding instruction
// (there will always be one, i.e. BUNDLE, if nothing else).
- assert(MI->isBundledWithPred());
- if (MI->isBundledWithSucc()) {
- MI->clearFlag(MachineInstr::BundledSucc);
- MI->clearFlag(MachineInstr::BundledPred);
+ assert(MI.isBundledWithPred());
+ if (MI.isBundledWithSucc()) {
+ MI.clearFlag(MachineInstr::BundledSucc);
+ MI.clearFlag(MachineInstr::BundledPred);
} else {
// If it's not bundled with the successor (i.e. it is the last one
// in the bundle), then we can simply unbundle it from the predecessor,
// which will take care of updating the predecessor's flag.
- MI->unbundleFromPred();
+ MI.unbundleFromPred();
}
- B.splice(InsertPt, &B, MI);
+ B.splice(InsertPt, &B, MI.getIterator());
// Get the size of the bundle without asserting.
MachineBasicBlock::const_instr_iterator I = BundleIt.getInstrIterator();
@@ -163,9 +163,9 @@
// Otherwise, extract the single instruction out and delete the bundle.
MachineBasicBlock::iterator NextIt = std::next(BundleIt);
- MachineInstr *SingleI = BundleIt->getNextNode();
- SingleI->unbundleFromPred();
- assert(!SingleI->isBundledWithSucc());
+ MachineInstr &SingleI = *BundleIt->getNextNode();
+ SingleI.unbundleFromPred();
+ assert(!SingleI.isBundledWithSucc());
BundleIt->eraseFromParent();
return NextIt;
}
@@ -266,7 +266,7 @@
}
-bool HexagonPacketizerList::isCallDependent(const MachineInstr* MI,
+bool HexagonPacketizerList::isCallDependent(const MachineInstr &MI,
SDep::Kind DepType, unsigned DepReg) {
// Check for LR dependence.
if (DepReg == HRI->getRARegister())
@@ -283,7 +283,7 @@
// Assumes that the first operand of the CALLr is the function address.
if (HII->isIndirectCall(MI) && (DepType == SDep::Data)) {
- MachineOperand MO = MI->getOperand(0);
+ MachineOperand MO = MI.getOperand(0);
if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg))
return true;
}
@@ -296,29 +296,29 @@
DepType == SDep::Output;
}
-static bool isDirectJump(const MachineInstr* MI) {
- return MI->getOpcode() == Hexagon::J2_jump;
+static bool isDirectJump(const MachineInstr &MI) {
+ return MI.getOpcode() == Hexagon::J2_jump;
}
-static bool isSchedBarrier(const MachineInstr* MI) {
- switch (MI->getOpcode()) {
+static bool isSchedBarrier(const MachineInstr &MI) {
+ switch (MI.getOpcode()) {
case Hexagon::Y2_barrier:
return true;
}
return false;
}
-static bool isControlFlow(const MachineInstr* MI) {
- return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
+static bool isControlFlow(const MachineInstr &MI) {
+ return MI.getDesc().isTerminator() || MI.getDesc().isCall();
}
/// Returns true if the instruction modifies a callee-saved register.
-static bool doesModifyCalleeSavedReg(const MachineInstr *MI,
+static bool doesModifyCalleeSavedReg(const MachineInstr &MI,
const TargetRegisterInfo *TRI) {
- const MachineFunction &MF = *MI->getParent()->getParent();
+ const MachineFunction &MF = *MI.getParent()->getParent();
for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
- if (MI->modifiesRegister(*CSR, TRI))
+ if (MI.modifiesRegister(*CSR, TRI))
return true;
return false;
}
@@ -326,30 +326,30 @@
// TODO: MI->isIndirectBranch() and IsRegisterJump(MI)
// Returns true if an instruction can be promoted to .new predicate or
// new-value store.
-bool HexagonPacketizerList::isNewifiable(const MachineInstr* MI,
+bool HexagonPacketizerList::isNewifiable(const MachineInstr &MI,
const TargetRegisterClass *NewRC) {
// Vector stores can be predicated, and can be new-value stores, but
// they cannot be predicated on a .new predicate value.
if (NewRC == &Hexagon::PredRegsRegClass)
- if (HII->isV60VectorInstruction(MI) && MI->mayStore())
+ if (HII->isV60VectorInstruction(MI) && MI.mayStore())
return false;
- return HII->isCondInst(MI) || MI->isReturn() || HII->mayBeNewStore(MI);
+ return HII->isCondInst(MI) || MI.isReturn() || HII->mayBeNewStore(MI);
}
// Promote an instructiont to its .cur form.
// At this time, we have already made a call to canPromoteToDotCur and made
// sure that it can *indeed* be promoted.
-bool HexagonPacketizerList::promoteToDotCur(MachineInstr* MI,
+bool HexagonPacketizerList::promoteToDotCur(MachineInstr &MI,
SDep::Kind DepType, MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC) {
assert(DepType == SDep::Data);
int CurOpcode = HII->getDotCurOp(MI);
- MI->setDesc(HII->get(CurOpcode));
+ MI.setDesc(HII->get(CurOpcode));
return true;
}
void HexagonPacketizerList::cleanUpDotCur() {
- MachineInstr *MI = NULL;
+ MachineInstr *MI = nullptr;
for (auto BI : CurrentPacketMIs) {
DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
if (BI->getOpcode() == Hexagon::V6_vL32b_cur_ai) {
@@ -370,12 +370,12 @@
}
// Check to see if an instruction can be dot cur.
-bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr *MI,
+bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI,
const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
const TargetRegisterClass *RC) {
if (!HII->isV60VectorInstruction(MI))
return false;
- if (!HII->isV60VectorInstruction(&*MII))
+ if (!HII->isV60VectorInstruction(*MII))
return false;
// Already a dot new instruction.
@@ -391,14 +391,14 @@
// Make sure candidate instruction uses cur.
DEBUG(dbgs() << "Can we DOT Cur Vector MI\n";
- MI->dump();
+ MI.dump();
dbgs() << "in packet\n";);
MachineInstr &MJ = *MII;
DEBUG({
dbgs() << "Checking CUR against ";
MJ.dump();
});
- unsigned DestReg = MI->getOperand(0).getReg();
+ unsigned DestReg = MI.getOperand(0).getReg();
bool FoundMatch = false;
for (auto &MO : MJ.operands())
if (MO.isReg() && MO.getReg() == DestReg)
@@ -414,7 +414,7 @@
return false;
}
- DEBUG(dbgs() << "Can Dot CUR MI\n"; MI->dump(););
+ DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump(););
// We can convert the opcode into a .cur.
return true;
}
@@ -422,7 +422,7 @@
// Promote an instruction to its .new form. At this time, we have already
// made a call to canPromoteToDotNew and made sure that it can *indeed* be
// promoted.
-bool HexagonPacketizerList::promoteToDotNew(MachineInstr* MI,
+bool HexagonPacketizerList::promoteToDotNew(MachineInstr &MI,
SDep::Kind DepType, MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC) {
assert (DepType == SDep::Data);
@@ -431,18 +431,18 @@
NewOpcode = HII->getDotNewPredOp(MI, MBPI);
else
NewOpcode = HII->getDotNewOp(MI);
- MI->setDesc(HII->get(NewOpcode));
+ MI.setDesc(HII->get(NewOpcode));
return true;
}
-bool HexagonPacketizerList::demoteToDotOld(MachineInstr* MI) {
- int NewOpcode = HII->getDotOldOp(MI->getOpcode());
- MI->setDesc(HII->get(NewOpcode));
+bool HexagonPacketizerList::demoteToDotOld(MachineInstr &MI) {
+ int NewOpcode = HII->getDotOldOp(MI.getOpcode());
+ MI.setDesc(HII->get(NewOpcode));
return true;
}
-bool HexagonPacketizerList::useCallersSP(MachineInstr *MI) {
- unsigned Opc = MI->getOpcode();
+bool HexagonPacketizerList::useCallersSP(MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::S2_storerd_io:
case Hexagon::S2_storeri_io:
@@ -453,7 +453,7 @@
llvm_unreachable("Unexpected instruction");
}
unsigned FrameSize = MF.getFrameInfo().getStackSize();
- MachineOperand &Off = MI->getOperand(1);
+ MachineOperand &Off = MI.getOperand(1);
int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
if (HII->isValidOffset(Opc, NewOff)) {
Off.setImm(NewOff);
@@ -462,8 +462,8 @@
return false;
}
-void HexagonPacketizerList::useCalleesSP(MachineInstr *MI) {
- unsigned Opc = MI->getOpcode();
+void HexagonPacketizerList::useCalleesSP(MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::S2_storerd_io:
case Hexagon::S2_storeri_io:
@@ -474,7 +474,7 @@
llvm_unreachable("Unexpected instruction");
}
unsigned FrameSize = MF.getFrameInfo().getStackSize();
- MachineOperand &Off = MI->getOperand(1);
+ MachineOperand &Off = MI.getOperand(1);
Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
}
@@ -495,30 +495,30 @@
return PK_False;
}
-static const MachineOperand &getPostIncrementOperand(const MachineInstr *MI,
+static const MachineOperand &getPostIncrementOperand(const MachineInstr &MI,
const HexagonInstrInfo *HII) {
- assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
+ assert(HII->isPostIncrement(&MI) && "Not a post increment operation.");
#ifndef NDEBUG
// Post Increment means duplicates. Use dense map to find duplicates in the
// list. Caution: Densemap initializes with the minimum of 64 buckets,
// whereas there are at most 5 operands in the post increment.
DenseSet<unsigned> DefRegsSet;
- for (auto &MO : MI->operands())
+ for (auto &MO : MI.operands())
if (MO.isReg() && MO.isDef())
DefRegsSet.insert(MO.getReg());
- for (auto &MO : MI->operands())
+ for (auto &MO : MI.operands())
if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
return MO;
#else
- if (MI->mayLoad()) {
- const MachineOperand &Op1 = MI->getOperand(1);
+ if (MI.mayLoad()) {
+ const MachineOperand &Op1 = MI.getOperand(1);
// The 2nd operand is always the post increment operand in load.
assert(Op1.isReg() && "Post increment operand has be to a register.");
return Op1;
}
- if (MI->getDesc().mayStore()) {
- const MachineOperand &Op0 = MI->getOperand(0);
+ if (MI.getDesc().mayStore()) {
+ const MachineOperand &Op0 = MI.getOperand(0);
// The 1st operand is always the post increment operand in store.
assert(Op0.isReg() && "Post increment operand has be to a register.");
return Op0;
@@ -529,13 +529,13 @@
}
// Get the value being stored.
-static const MachineOperand& getStoreValueOperand(const MachineInstr *MI) {
+static const MachineOperand& getStoreValueOperand(const MachineInstr &MI) {
// value being stored is always the last operand.
- return MI->getOperand(MI->getNumOperands()-1);
+ return MI.getOperand(MI.getNumOperands()-1);
}
-static bool isLoadAbsSet(const MachineInstr *MI) {
- unsigned Opc = MI->getOpcode();
+static bool isLoadAbsSet(const MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::L4_loadrd_ap:
case Hexagon::L4_loadrb_ap:
@@ -548,9 +548,9 @@
return false;
}
-static const MachineOperand &getAbsSetOperand(const MachineInstr *MI) {
+static const MachineOperand &getAbsSetOperand(const MachineInstr &MI) {
assert(isLoadAbsSet(MI));
- return MI->getOperand(1);
+ return MI.getOperand(1);
}
@@ -571,8 +571,8 @@
// if there is a new value store in the packet. Corollary: if there is
// already a store in a packet, there can not be a new value store.
// Arch Spec: 3.4.4.2
-bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr *MI,
- const MachineInstr *PacketMI, unsigned DepReg) {
+bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
+ const MachineInstr &PacketMI, unsigned DepReg) {
// Make sure we are looking at the store, that can be promoted.
if (!HII->mayBeNewStore(MI))
return false;
@@ -582,7 +582,7 @@
if (Val.isReg() && Val.getReg() != DepReg)
return false;
- const MCInstrDesc& MCID = PacketMI->getDesc();
+ const MCInstrDesc& MCID = PacketMI.getDesc();
// First operand is always the result.
const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
@@ -600,12 +600,12 @@
// Make sure it's NOT the post increment register that we are going to
// new value.
- if (HII->isPostIncrement(MI) &&
+ if (HII->isPostIncrement(&MI) &&
getPostIncrementOperand(MI, HII).getReg() == DepReg) {
return false;
}
- if (HII->isPostIncrement(PacketMI) && PacketMI->mayLoad() &&
+ if (HII->isPostIncrement(&PacketMI) && PacketMI.mayLoad() &&
getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
// If source is post_inc, or absolute-set addressing, it can not feed
// into new value store
@@ -620,8 +620,8 @@
// If the source that feeds the store is predicated, new value store must
// also be predicated.
- if (HII->isPredicated(*PacketMI)) {
- if (!HII->isPredicated(*MI))
+ if (HII->isPredicated(PacketMI)) {
+ if (!HII->isPredicated(MI))
return false;
// Check to make sure that they both will have their predicates
@@ -631,7 +631,7 @@
const TargetRegisterClass* predRegClass = nullptr;
// Get predicate register used in the source instruction.
- for (auto &MO : PacketMI->operands()) {
+ for (auto &MO : PacketMI.operands()) {
if (!MO.isReg())
continue;
predRegNumSrc = MO.getReg();
@@ -643,7 +643,7 @@
"predicate register not found in a predicated PacketMI instruction");
// Get predicate register used in new-value store instruction.
- for (auto &MO : MI->operands()) {
+ for (auto &MO : MI.operands()) {
if (!MO.isReg())
continue;
predRegNumDst = MO.getReg();
@@ -664,7 +664,7 @@
// sense, i.e, either both should be negated or both should be non-negated.
if (predRegNumDst != predRegNumSrc ||
HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
- getPredicateSense(*MI, HII) != getPredicateSense(*PacketMI, HII))
+ getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
return false;
}
@@ -680,19 +680,19 @@
for (auto I : CurrentPacketMIs) {
SUnit *TempSU = MIToSUnit.find(I)->second;
- MachineInstr* TempMI = TempSU->getInstr();
+ MachineInstr &TempMI = *TempSU->getInstr();
// Following condition is true for all the instructions until PacketMI is
// reached (StartCheck is set to 0 before the for loop).
// StartCheck flag is 1 for all the instructions after PacketMI.
- if (TempMI != PacketMI && !StartCheck) // Start processing only after
- continue; // encountering PacketMI.
+ if (&TempMI != &PacketMI && !StartCheck) // Start processing only after
+ continue; // encountering PacketMI.
StartCheck = 1;
- if (TempMI == PacketMI) // We don't want to check PacketMI for dependence.
+ if (&TempMI == &PacketMI) // We don't want to check PacketMI for dependence.
continue;
- for (auto &MO : MI->operands())
+ for (auto &MO : MI.operands())
if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
return false;
}
@@ -703,9 +703,9 @@
// The following store can not be dot new.
// Eg. r0 = add(r0, #3)
// memw(r1+r0<<#2) = r0
- if (!HII->isPostIncrement(MI)) {
- for (unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
- const MachineOperand &MO = MI->getOperand(opNum);
+ if (!HII->isPostIncrement(&MI)) {
+ for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
+ const MachineOperand &MO = MI.getOperand(opNum);
if (MO.isReg() && MO.getReg() == DepReg)
return false;
}
@@ -715,7 +715,7 @@
// do not newify the store. Eg.
// %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
// S2_storerh_io %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
- for (auto &MO : PacketMI->operands()) {
+ for (auto &MO : PacketMI.operands()) {
if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
continue;
unsigned R = MO.getReg();
@@ -728,7 +728,7 @@
// just-in-case. For example, we cannot newify R2 in the following case:
// %R3<def> = A2_tfrsi 0;
// S2_storeri_io %R0<kill>, 0, %R2<kill>, %D1<imp-use,kill>;
- for (auto &MO : MI->operands()) {
+ for (auto &MO : MI.operands()) {
if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
return false;
}
@@ -738,14 +738,14 @@
}
// Can this MI to promoted to either new value store or new value jump.
-bool HexagonPacketizerList::canPromoteToNewValue(const MachineInstr *MI,
+bool HexagonPacketizerList::canPromoteToNewValue(const MachineInstr &MI,
const SUnit *PacketSU, unsigned DepReg,
MachineBasicBlock::iterator &MII) {
if (!HII->mayBeNewStore(MI))
return false;
// Check to see the store can be new value'ed.
- MachineInstr *PacketMI = PacketSU->getInstr();
+ MachineInstr &PacketMI = *PacketSU->getInstr();
if (canPromoteToNewValueStore(MI, PacketMI, DepReg))
return true;
@@ -754,8 +754,8 @@
return false;
}
-static bool isImplicitDependency(const MachineInstr *I, unsigned DepReg) {
- for (auto &MO : I->operands())
+static bool isImplicitDependency(const MachineInstr &I, unsigned DepReg) {
+ for (auto &MO : I.operands())
if (MO.isReg() && MO.isDef() && (MO.getReg() == DepReg) && MO.isImplicit())
return true;
return false;
@@ -766,7 +766,7 @@
// 1. dot new on predicate - V2/V3/V4
// 2. dot new on stores NV/ST - V4
// 3. dot new on jump NV/J - V4 -- This is generated in a pass.
-bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr *MI,
+bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI,
const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC) {
// Already a dot new instruction.
@@ -776,15 +776,15 @@
if (!isNewifiable(MI, RC))
return false;
- const MachineInstr *PI = PacketSU->getInstr();
+ const MachineInstr &PI = *PacketSU->getInstr();
// The "new value" cannot come from inline asm.
- if (PI->isInlineAsm())
+ if (PI.isInlineAsm())
return false;
// IMPLICIT_DEFs won't materialize as real instructions, so .new makes no
// sense.
- if (PI->isImplicitDef())
+ if (PI.isImplicitDef())
return false;
// If dependency is trough an implicitly defined register, we should not
@@ -792,7 +792,7 @@
if (isImplicitDependency(PI, DepReg))
return false;
- const MCInstrDesc& MCID = PI->getDesc();
+ const MCInstrDesc& MCID = PI.getDesc();
const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
if (DisableVecDblNVStores && VecRC == &Hexagon::VecDblRegsRegClass)
return false;
@@ -801,7 +801,7 @@
// bug 5670: until that is fixed
// TODO: MI->isIndirectBranch() and IsRegisterJump(MI)
if (RC == &Hexagon::PredRegsRegClass)
- if (HII->isCondInst(MI) || MI->isReturn())
+ if (HII->isCondInst(MI) || MI.isReturn())
return HII->predCanBeUsedAsDotNew(PI, DepReg);
if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
@@ -837,9 +837,9 @@
// The P3 from a) and d) will be complements after
// a)'s P3 is converted to .new form
// Anti-dep between c) and b) is irrelevant for this case
-bool HexagonPacketizerList::restrictingDepExistInPacket(MachineInstr* MI,
+bool HexagonPacketizerList::restrictingDepExistInPacket(MachineInstr &MI,
unsigned DepReg) {
- SUnit *PacketSUDep = MIToSUnit.find(MI)->second;
+ SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
for (auto I : CurrentPacketMIs) {
// We only care for dependencies to predicated instructions
@@ -931,7 +931,7 @@
// above example. Now I need to see if there is an anti dependency
// from c) to any other instruction in the same packet on the pred
// reg of interest.
- if (restrictingDepExistInPacket(I, Dep.getReg()))
+ if (restrictingDepExistInPacket(*I, Dep.getReg()))
return false;
}
}
@@ -948,7 +948,7 @@
Hexagon::PredRegsRegClass.contains(PReg1) &&
Hexagon::PredRegsRegClass.contains(PReg2) &&
getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
- HII->isDotNewInst(&MI1) == HII->isDotNewInst(&MI2);
+ HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
}
// Initialize packetizer flags.
@@ -999,10 +999,10 @@
// From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
// trap, pause, barrier, icinva, isync, and syncht are solo instructions.
// They must not be grouped with other instructions in a packet.
- if (isSchedBarrier(&MI))
+ if (isSchedBarrier(MI))
return true;
- if (HII->isSolo(&MI))
+ if (HII->isSolo(MI))
return true;
if (MI.getOpcode() == Hexagon::A2_nop)
@@ -1019,9 +1019,9 @@
// cannotCoexistAsymm(MI, MJ) || cannotCoexistAsymm(MJ, MI)
// Doing the test only one way saves the amount of code in this function,
// since every test would need to be repeated with the MI and MJ reversed.
-static bool cannotCoexistAsymm(const MachineInstr *MI, const MachineInstr *MJ,
+static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
const HexagonInstrInfo &HII) {
- const MachineFunction *MF = MI->getParent()->getParent();
+ const MachineFunction *MF = MI.getParent()->getParent();
if (MF->getSubtarget<HexagonSubtarget>().hasV60TOpsOnly() &&
HII.isHVXMemWithAIndirect(MI, MJ))
return true;
@@ -1030,9 +1030,9 @@
// able to remove the asm out after packetizing (i.e. if the asm must be
// moved past the bundle). Similarly, two asms cannot be together to avoid
// complications when determining their relative order outside of a bundle.
- if (MI->isInlineAsm())
- return MJ->isInlineAsm() || MJ->isBranch() || MJ->isBarrier() ||
- MJ->isCall() || MJ->isTerminator();
+ if (MI.isInlineAsm())
+ return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
+ MJ.isCall() || MJ.isTerminator();
// "False" really means that the quick check failed to determine if
// I and J cannot coexist.
@@ -1041,8 +1041,8 @@
// Full, symmetric check.
-bool HexagonPacketizerList::cannotCoexist(const MachineInstr *MI,
- const MachineInstr *MJ) {
+bool HexagonPacketizerList::cannotCoexist(const MachineInstr &MI,
+ const MachineInstr &MJ) {
return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
}
@@ -1052,10 +1052,10 @@
MachineBasicBlock::instr_iterator NextI;
for (auto I = B.instr_begin(), E = B.instr_end(); I != E; I = NextI) {
NextI = std::next(I);
- MachineInstr *MI = &*I;
- if (MI->isBundle())
+ MachineInstr &MI = *I;
+ if (MI.isBundle())
BundleIt = I;
- if (!MI->isInsideBundle())
+ if (!MI.isInsideBundle())
continue;
// Decide on where to insert the instruction that we are pulling out.
@@ -1065,9 +1065,9 @@
// other instructions in the bundle read, then we need to place it
// after the bundle (to preserve the bundle semantics).
bool InsertBeforeBundle;
- if (MI->isInlineAsm())
- InsertBeforeBundle = !hasWriteToReadDep(*MI, *BundleIt, HRI);
- else if (MI->isDebugValue())
+ if (MI.isInlineAsm())
+ InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
+ else if (MI.isDebugValue())
InsertBeforeBundle = true;
else
continue;
@@ -1078,8 +1078,8 @@
}
// Check if a given instruction is of class "system".
-static bool isSystemInstr(const MachineInstr *MI) {
- unsigned Opc = MI->getOpcode();
+static bool isSystemInstr(const MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::Y2_barrier:
case Hexagon::Y2_dcfetchbo:
@@ -1088,24 +1088,24 @@
return false;
}
-bool HexagonPacketizerList::hasDeadDependence(const MachineInstr *I,
- const MachineInstr *J) {
+bool HexagonPacketizerList::hasDeadDependence(const MachineInstr &I,
+ const MachineInstr &J) {
// The dependence graph may not include edges between dead definitions,
// so without extra checks, we could end up packetizing two instruction
// defining the same (dead) register.
- if (I->isCall() || J->isCall())
+ if (I.isCall() || J.isCall())
return false;
- if (HII->isPredicated(*I) || HII->isPredicated(*J))
+ if (HII->isPredicated(I) || HII->isPredicated(J))
return false;
BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
- for (auto &MO : I->operands()) {
+ for (auto &MO : I.operands()) {
if (!MO.isReg() || !MO.isDef() || !MO.isDead())
continue;
DeadDefs[MO.getReg()] = true;
}
- for (auto &MO : J->operands()) {
+ for (auto &MO : J.operands()) {
if (!MO.isReg() || !MO.isDef() || !MO.isDead())
continue;
unsigned R = MO.getReg();
@@ -1115,8 +1115,8 @@
return false;
}
-bool HexagonPacketizerList::hasControlDependence(const MachineInstr *I,
- const MachineInstr *J) {
+bool HexagonPacketizerList::hasControlDependence(const MachineInstr &I,
+ const MachineInstr &J) {
// A save callee-save register function call can only be in a packet
// with instructions that don't write to the callee-save registers.
if ((HII->isSaveCalleeSavedRegsCall(I) &&
@@ -1132,10 +1132,10 @@
// \ref-manual (7.3.4) A loop setup packet in loopN or spNloop0 cannot
// contain a speculative indirect jump,
// a new-value compare jump or a dealloc_return.
- auto isBadForLoopN = [this] (const MachineInstr *MI) -> bool {
- if (MI->isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
+ auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {
+ if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
return true;
- if (HII->isPredicated(*MI) && HII->isPredicatedNew(*MI) && HII->isJumpR(MI))
+ if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
return true;
return false;
};
@@ -1148,13 +1148,13 @@
// dealloc_return cannot appear in the same packet as a conditional or
// unconditional jump.
return HII->isDeallocRet(I) &&
- (J->isBranch() || J->isCall() || J->isBarrier());
+ (J.isBranch() || J.isCall() || J.isBarrier());
}
-bool HexagonPacketizerList::hasV4SpecificDependence(const MachineInstr *I,
- const MachineInstr *J) {
+bool HexagonPacketizerList::hasV4SpecificDependence(const MachineInstr &I,
+ const MachineInstr &J) {
bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J);
- bool StoreI = I->mayStore(), StoreJ = J->mayStore();
+ bool StoreI = I.mayStore(), StoreJ = J.mayStore();
if ((SysI && StoreJ) || (SysJ && StoreI))
return true;
@@ -1177,18 +1177,18 @@
// SUJ is the current instruction inside the current packet against which that
// SUI will be packetized.
bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
- MachineInstr *I = SUI->getInstr();
- MachineInstr *J = SUJ->getInstr();
- assert(I && J && "Unable to packetize null instruction!");
+ assert(SUI->getInstr() && SUJ->getInstr());
+ MachineInstr &I = *SUI->getInstr();
+ MachineInstr &J = *SUJ->getInstr();
// Clear IgnoreDepMIs when Packet starts.
if (CurrentPacketMIs.size() == 1)
IgnoreDepMIs.clear();
- MachineBasicBlock::iterator II = I;
+ MachineBasicBlock::iterator II = I.getIterator();
// Solo instructions cannot go in the packet.
- assert(!isSoloInstruction(*I) && "Unexpected solo instr!");
+ assert(!isSoloInstruction(I) && "Unexpected solo instr!");
if (cannotCoexist(I, J))
return false;
@@ -1205,23 +1205,23 @@
return false;
// If an instruction feeds new value jump, glue it.
- MachineBasicBlock::iterator NextMII = I;
+ MachineBasicBlock::iterator NextMII = I.getIterator();
++NextMII;
- if (NextMII != I->getParent()->end() && HII->isNewValueJump(&*NextMII)) {
+ if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
MachineInstr &NextMI = *NextMII;
bool secondRegMatch = false;
const MachineOperand &NOp0 = NextMI.getOperand(0);
const MachineOperand &NOp1 = NextMI.getOperand(1);
- if (NOp1.isReg() && I->getOperand(0).getReg() == NOp1.getReg())
+ if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
secondRegMatch = true;
- for (auto I : CurrentPacketMIs) {
- SUnit *PacketSU = MIToSUnit.find(I)->second;
- MachineInstr *PI = PacketSU->getInstr();
+ for (auto T : CurrentPacketMIs) {
+ SUnit *PacketSU = MIToSUnit.find(T)->second;
+ MachineInstr &PI = *PacketSU->getInstr();
// NVJ can not be part of the dual jump - Arch Spec: section 7.8.
- if (PI->isCall()) {
+ if (PI.isCall()) {
Dependence = true;
break;
}
@@ -1233,14 +1233,14 @@
// 3. If the second operand of the nvj is newified, (which means
// first operand is also a reg), first reg is not defined in
// the same packet.
- if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||
+ if (PI.getOpcode() == Hexagon::S2_allocframe || PI.mayStore() ||
HII->isLoopN(PI)) {
Dependence = true;
break;
}
// Check #2/#3.
const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
- if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
+ if (OpR.isReg() && PI.modifiesRegister(OpR.getReg(), HRI)) {
Dependence = true;
break;
}
@@ -1291,7 +1291,7 @@
RC = HRI->getMinimalPhysRegClass(DepReg);
}
- if (I->isCall() || I->isReturn() || HII->isTailCall(I)) {
+ if (I.isCall() || I.isReturn() || HII->isTailCall(I)) {
if (!isRegDependence(DepType))
continue;
if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
@@ -1324,8 +1324,8 @@
// For predicated instructions, if the predicates are complements then
// there can be no dependence.
- if (HII->isPredicated(*I) && HII->isPredicated(*J) &&
- arePredicatesComplements(*I, *J)) {
+ if (HII->isPredicated(I) && HII->isPredicated(J) &&
+ arePredicatesComplements(I, J)) {
// Not always safe to do this translation.
// DAG Builder attempts to reduce dependence edges using transitive
// nature of dependencies. Here is an example:
@@ -1338,24 +1338,24 @@
// However, there is no dependence edge between (1)->(3). This results
// in all 3 instructions going in the same packet. We ignore dependce
// only once to avoid this situation.
- auto Itr = std::find(IgnoreDepMIs.begin(), IgnoreDepMIs.end(), J);
+ auto Itr = std::find(IgnoreDepMIs.begin(), IgnoreDepMIs.end(), &J);
if (Itr != IgnoreDepMIs.end()) {
Dependence = true;
return false;
}
- IgnoreDepMIs.push_back(I);
+ IgnoreDepMIs.push_back(&I);
continue;
}
// Ignore Order dependences between unconditional direct branches
// and non-control-flow instructions.
- if (isDirectJump(I) && !J->isBranch() && !J->isCall() &&
+ if (isDirectJump(I) && !J.isBranch() && !J.isCall() &&
DepType == SDep::Order)
continue;
// Ignore all dependences for jumps except for true and output
// dependences.
- if (I->isConditionalBranch() && DepType != SDep::Data &&
+ if (I.isConditionalBranch() && DepType != SDep::Data &&
DepType != SDep::Output)
continue;
@@ -1377,7 +1377,7 @@
unsigned DepReg = SUJ->Succs[i].getReg();
// Check if I and J really defines DepReg.
- if (!I->definesRegister(DepReg) && !J->definesRegister(DepReg))
+ if (!I.definesRegister(DepReg) && !J.definesRegister(DepReg))
continue;
FoundSequentialDependence = true;
break;
@@ -1391,15 +1391,15 @@
// 4. Load followed by any memory operation is allowed.
if (DepType == SDep::Order) {
if (!PacketizeVolatiles) {
- bool OrdRefs = I->hasOrderedMemoryRef() || J->hasOrderedMemoryRef();
+ bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
if (OrdRefs) {
FoundSequentialDependence = true;
break;
}
}
// J is first, I is second.
- bool LoadJ = J->mayLoad(), StoreJ = J->mayStore();
- bool LoadI = I->mayLoad(), StoreI = I->mayStore();
+ bool LoadJ = J.mayLoad(), StoreJ = J.mayStore();
+ bool LoadI = I.mayLoad(), StoreI = I.mayStore();
if (StoreJ) {
// Two stores are only allowed on V4+. Load following store is never
// allowed.
@@ -1424,14 +1424,14 @@
// between ALLOCFRAME and subsequent store, allow it to be packetized
// in a same packet. This implies that the store is using the caller's
// SP. Hence, offset needs to be updated accordingly.
- if (DepType == SDep::Data && J->getOpcode() == Hexagon::S2_allocframe) {
- unsigned Opc = I->getOpcode();
+ if (DepType == SDep::Data && J.getOpcode() == Hexagon::S2_allocframe) {
+ unsigned Opc = I.getOpcode();
switch (Opc) {
case Hexagon::S2_storerd_io:
case Hexagon::S2_storeri_io:
case Hexagon::S2_storerh_io:
case Hexagon::S2_storerb_io:
- if (I->getOperand(0).getReg() == HRI->getStackRegister()) {
+ if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
// Since this store is to be glued with allocframe in the same
// packet, it will use SP of the previous stack frame, i.e.
// caller's SP. Therefore, we need to recalculate offset
@@ -1451,12 +1451,12 @@
// R0 = ... ; SUI
// Those cannot be packetized together, since the call will observe
// the effect of the assignment to R0.
- if (DepType == SDep::Anti && J->isCall()) {
+ if (DepType == SDep::Anti && J.isCall()) {
// Check if I defines any volatile register. We should also check
// registers that the call may read, but these happen to be a
// subset of the volatile register set.
- for (const MCPhysReg *P = J->getDesc().ImplicitDefs; P && *P; ++P) {
- if (!I->modifiesRegister(*P, HRI))
+ for (const MCPhysReg *P = J.getDesc().ImplicitDefs; P && *P; ++P) {
+ if (!I.modifiesRegister(*P, HRI))
continue;
FoundSequentialDependence = true;
break;
@@ -1484,9 +1484,9 @@
}
bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
- MachineInstr *I = SUI->getInstr();
- MachineInstr *J = SUJ->getInstr();
- assert(I && J && "Unable to packetize null instruction!");
+ assert(SUI->getInstr() && SUJ->getInstr());
+ MachineInstr &I = *SUI->getInstr();
+ MachineInstr &J = *SUJ->getInstr();
if (cannotCoexist(I, J))
return false;
@@ -1512,7 +1512,7 @@
MachineBasicBlock::iterator
HexagonPacketizerList::addToPacket(MachineInstr &MI) {
- MachineBasicBlock::iterator MII = MI;
+ MachineBasicBlock::iterator MII = MI.getIterator();
MachineBasicBlock *MBB = MI.getParent();
if (MI.isImplicitDef()) {
unsigned R = MI.getOperand(0).getReg();
@@ -1524,7 +1524,7 @@
}
assert(ResourceTracker->canReserveResources(MI));
- bool ExtMI = HII->isExtended(&MI) || HII->isConstExtended(&MI);
+ bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
bool Good = true;
if (GlueToNewValueJump) {
@@ -1537,7 +1537,7 @@
if (ExtMI)
Good = tryAllocateResourcesForConstExt(true);
- bool ExtNvjMI = HII->isExtended(&NvjMI) || HII->isConstExtended(&NvjMI);
+ bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
if (Good) {
if (ResourceTracker->canReserveResources(NvjMI))
ResourceTracker->reserveResources(NvjMI);
@@ -1571,9 +1571,9 @@
if (ExtMI && !tryAllocateResourcesForConstExt(true)) {
endPacket(MBB, MI);
if (PromotedToDotNew)
- demoteToDotOld(&MI);
+ demoteToDotOld(MI);
if (GlueAllocframeStore) {
- useCalleesSP(&MI);
+ useCalleesSP(MI);
GlueAllocframeStore = false;
}
ResourceTracker->reserveResources(MI);
@@ -1591,18 +1591,18 @@
}
bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) {
- return !producesStall(&MI);
+ return !producesStall(MI);
}
// Return true when ConsMI uses a register defined by ProdMI.
-static bool isDependent(const MachineInstr *ProdMI,
- const MachineInstr *ConsMI) {
- if (!ProdMI->getOperand(0).isReg())
+static bool isDependent(const MachineInstr &ProdMI,
+ const MachineInstr &ConsMI) {
+ if (!ProdMI.getOperand(0).isReg())
return false;
- unsigned DstReg = ProdMI->getOperand(0).getReg();
+ unsigned DstReg = ProdMI.getOperand(0).getReg();
- for (auto &Op : ConsMI->operands())
+ for (auto &Op : ConsMI.operands())
if (Op.isReg() && Op.isUse() && Op.getReg() == DstReg)
// The MIs depend on each other.
return true;
@@ -1611,7 +1611,7 @@
}
// V60 forward scheduling.
-bool HexagonPacketizerList::producesStall(const MachineInstr *I) {
+bool HexagonPacketizerList::producesStall(const MachineInstr &I) {
// Check whether the previous packet is in a different loop. If this is the
// case, there is little point in trying to avoid a stall because that would
// favor the rare case (loop entry) over the common case (loop iteration).
@@ -1621,7 +1621,7 @@
// backedge.
if (!OldPacketMIs.empty()) {
auto *OldBB = OldPacketMIs.front()->getParent();
- auto *ThisBB = I->getParent();
+ auto *ThisBB = I.getParent();
if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))
return false;
}
@@ -1629,9 +1629,9 @@
// Check for stall between two vector instructions.
if (HII->isV60VectorInstruction(I)) {
for (auto J : OldPacketMIs) {
- if (!HII->isV60VectorInstruction(J))
+ if (!HII->isV60VectorInstruction(*J))
continue;
- if (isDependent(J, I) && !HII->isVecUsableNextPacket(J, I))
+ if (isDependent(*J, I) && !HII->isVecUsableNextPacket(*J, I))
return true;
}
return false;
@@ -1641,17 +1641,17 @@
// there is no definition of a use in the current packet, because it
// may be a candidate for .new.
for (auto J : CurrentPacketMIs)
- if (!HII->isV60VectorInstruction(J) && isDependent(J, I))
+ if (!HII->isV60VectorInstruction(*J) && isDependent(*J, I))
return false;
// Check for stall between I and instructions in the previous packet.
if (MF.getSubtarget<HexagonSubtarget>().useBSBScheduling()) {
for (auto J : OldPacketMIs) {
- if (HII->isV60VectorInstruction(J))
+ if (HII->isV60VectorInstruction(*J))
continue;
- if (!HII->isLateInstrFeedsEarlyInstr(J, I))
+ if (!HII->isLateInstrFeedsEarlyInstr(*J, I))
continue;
- if (isDependent(J, I) && !HII->canExecuteInBundle(J, I))
+ if (isDependent(*J, I) && !HII->canExecuteInBundle(*J, I))
return true;
}
}