commit f1d388a5c5a03696349959def898e4f23bffdbdc
author Igor Breger <igor.breger@intel.com> Sun Sep 17 11:34:17 2017 +0000
committer Igor Breger <igor.breger@intel.com> Sun Sep 17 11:34:17 2017 +0000
tree cfe8515ded9a47bd49b6825a99c6623afc23dcd6
parent e57308ecf0fad0f4dae56e43d3c76a3a47dde981

[GlobalISel][X86] Legalize i1 G_ADD/G_SUB/G_MUL/G_XOR/G_OR/G_AND instructions.

llvm-svn: 313483

llvm/lib/Target/X86/X86LegalizerInfo.cpp

diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
index 6bbb3f3..98b4863 100644
--- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
@@ -57,10 +57,13 @@
 
   setAction({G_PHI, s1}, WidenScalar);
 
-  for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
+  for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
     for (auto Ty : {s8, s16, s32})
       setAction({BinOp, Ty}, Legal);
 
+    setAction({BinOp, s1}, WidenScalar);
+  }
+
   for (unsigned Op : {G_UADDE}) {
     setAction({Op, s32}, Legal);
     setAction({Op, 1, s1}, Legal);