DAG->DAG instruction selection for ia64! "hello world" works, not much else.
use -enable-ia64-dag-isel to turn this on
TODO: delete lowering stuff from the pattern isel
: get operations on predicate bits working
: get other bits of pseudocode going
: use sampo's mulh/mull-using divide-by-constant magic
: *so* many patterns ("extr", "tbit" and "dep" will be fun :)
: add FP
: add a JIT!
: get it working 100%
in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.
OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.
llvm-svn: 24058
diff --git a/llvm/lib/Target/IA64/IA64TargetMachine.cpp b/llvm/lib/Target/IA64/IA64TargetMachine.cpp
index 7d80e57..3760f48 100644
--- a/llvm/lib/Target/IA64/IA64TargetMachine.cpp
+++ b/llvm/lib/Target/IA64/IA64TargetMachine.cpp
@@ -37,6 +37,9 @@
cl::desc("Disable the IA64 asm printer, for use "
"when profiling the code generator."));
+ cl::opt<bool> EnableDAGIsel("enable-ia64-dag-isel", cl::Hidden,
+ cl::desc("Enable the IA64 DAG->DAG isel"));
+
// Register the target.
RegisterTarget<IA64TargetMachine> X("ia64", " IA-64 (Itanium)");
}
@@ -97,8 +100,12 @@
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
- PM.add(createIA64PatternInstructionSelector(*this));
-
+ // Add an instruction selector
+ if(EnableDAGIsel)
+ PM.add(createIA64DAGToDAGInstructionSelector(*this));
+ else
+ PM.add(createIA64PatternInstructionSelector(*this));
+
/* XXX not yet. ;)
// Run optional SSA-based machine code optimizations next...
if (!NoSSAPeephole)