[Power9] Enable the Out-of-Order scheduling model for P9 hw
When switched to the MI scheduler for P9, the hardware is modeled as out of order.
However, inside the MI Scheduler algorithm, we still use the in-order scheduling model
as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer
the op. So, only when all the available instructions issued, the pending instruction
could be scheduled. That is not true for our P9 hw in fact.
This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is
picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017.
With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows:
x264_r: +6.95%
cactuBSSN_r: +6.94%
lbm_r: +4.11%
xz_r: -3.85%
And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved.
Reviewer: Nemanjai
Differential Revision: https://reviews.llvm.org/D55810
llvm-svn: 350285
diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
index d671c76..9d16103 100644
--- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
@@ -82,7 +82,6 @@
align 16 %a) {
; CHECK-LABEL: testStruct_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv v2, 128(r1)
; CHECK-NEXT: std r10, 88(r1)
; CHECK-NEXT: std r9, 80(r1)
; CHECK-NEXT: std r8, 72(r1)
@@ -91,11 +90,11 @@
; CHECK-NEXT: std r5, 48(r1)
; CHECK-NEXT: std r4, 40(r1)
; CHECK-NEXT: std r3, 32(r1)
+; CHECK-NEXT: lxv v2, 128(r1)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testStruct_03:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: lxv v2, 144(r1)
; CHECK-BE-NEXT: std r10, 104(r1)
; CHECK-BE-NEXT: std r9, 96(r1)
; CHECK-BE-NEXT: std r8, 88(r1)
@@ -104,6 +103,7 @@
; CHECK-BE-NEXT: std r5, 64(r1)
; CHECK-BE-NEXT: std r4, 56(r1)
; CHECK-BE-NEXT: std r3, 48(r1)
+; CHECK-BE-NEXT: lxv v2, 144(r1)
; CHECK-BE-NEXT: blr
entry:
%a7 = getelementptr inbounds %struct.With9fp128params,
@@ -228,12 +228,12 @@
define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) {
; CHECK-LABEL: testMixedAggregate_03:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: mtvsrwa v2, r3
-; CHECK-DAG: mtvsrdd v3, r6, r5
-; CHECK: mtvsrd v4, r10
+; CHECK: mtvsrwa v2, r3
; CHECK: xscvsdqp v2, v2
-; CHECK-DAG: xscvsdqp v[[REG:[0-9]+]], v4
-; CHECK-DAG: xsaddqp v2, v3, v2
+; CHECK: mtvsrdd v3, r6, r5
+; CHECK: xsaddqp v2, v3, v2
+; CHECK: mtvsrd v[[REG1:[0-9]+]], r10
+; CHECK: xscvsdqp v[[REG:[0-9]+]], v[[REG1]]
; CHECK: xsaddqp v2, v2, v[[REG]]
; CHECK-NEXT: blr
entry:
@@ -260,11 +260,11 @@
; CHECK-NEXT: std r7, 64(r1)
; CHECK-NEXT: std r10, 88(r1)
; CHECK-NEXT: std r9, 80(r1)
-; CHECK-NEXT: lxv v2, 64(r1)
; CHECK-NEXT: std r6, 56(r1)
; CHECK-NEXT: std r5, 48(r1)
; CHECK-NEXT: std r4, 40(r1)
; CHECK-NEXT: std r3, 32(r1)
+; CHECK-NEXT: lxv v2, 64(r1)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testNestedAggregate:
@@ -273,11 +273,11 @@
; CHECK-BE-NEXT: std r7, 80(r1)
; CHECK-BE-NEXT: std r10, 104(r1)
; CHECK-BE-NEXT: std r9, 96(r1)
-; CHECK-BE-NEXT: lxv v2, 80(r1)
; CHECK-BE-NEXT: std r6, 72(r1)
; CHECK-BE-NEXT: std r5, 64(r1)
; CHECK-BE-NEXT: std r4, 56(r1)
; CHECK-BE-NEXT: std r3, 48(r1)
+; CHECK-BE-NEXT: lxv v2, 80(r1)
; CHECK-BE-NEXT: blr
entry:
%c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
@@ -337,25 +337,25 @@
define fp128 @sum_float128(i32 signext %count, ...) {
; CHECK-LABEL: sum_float128:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r11, r2, .LCPI17_0@toc@ha
-; CHECK-NEXT: cmpwi cr0, r3, 1
; CHECK-NEXT: std r10, 88(r1)
; CHECK-NEXT: std r9, 80(r1)
; CHECK-NEXT: std r8, 72(r1)
; CHECK-NEXT: std r7, 64(r1)
; CHECK-NEXT: std r6, 56(r1)
-; CHECK-NEXT: std r5, 48(r1)
+; CHECK-NEXT: cmpwi cr0, r3, 1
; CHECK-NEXT: std r4, 40(r1)
-; CHECK-NEXT: addi r11, r11, .LCPI17_0@toc@l
-; CHECK-NEXT: lxvx v2, 0, r11
+; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
+; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l
+; CHECK-NEXT: lxvx v2, 0, [[REG1]]
+; CHECK-NEXT: std r5, 48(r1)
; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: addi r3, r1, 40
; CHECK-NEXT: lxvx v3, 0, r3
; CHECK-NEXT: xsaddqp v2, v3, v2
+; CHECK-NEXT: addi [[REG2:r[0-9]+]], r1, 72
+; CHECK-NEXT: std [[REG2]], -8(r1)
; CHECK-NEXT: lxv v3, 16(r3)
-; CHECK-NEXT: addi r3, r1, 72
-; CHECK-NEXT: std r3, -8(r1)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
entry: