commit f4760455e80a7c614edc72bdcbfa58eb10d92d35
author Matt Arsenault <Matthew.Arsenault@amd.com> Thu Nov 14 08:06:38 2013 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Thu Nov 14 08:06:38 2013 +0000
tree f0f99d5a531258c002abc45dd965f6ff938997b5
parent 269092d747506ca42e7a0f24a5fc9c7d674979fd

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llvm-svn: 194684

llvm/lib/Target/R600/SIInstrInfo.cpp

diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp
index e293c3a..8eb707d 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.cpp
+++ b/llvm/lib/Target/R600/SIInstrInfo.cpp
@@ -440,7 +440,9 @@
   // Legalize VOP2
   if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
     MachineOperand &Src1 = MI->getOperand(Src1Idx);
-    // Legalize VOP2 instructions where src1 is not a VGPR.
+
+    // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
+    // be the first operand, and there can only be one.
     if (Src1.isImm() || Src1.isFPImm() ||
         (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
       if (MI->isCommutable()) {