commit f4a6dd28b6a801d4c7dd8b8aaa33f54d2258171d
author Petar Avramovic <Petar.Avramovic@rt-rk.com> Fri May 31 08:06:17 2019 +0000
committer Petar Avramovic <Petar.Avramovic@rt-rk.com> Fri May 31 08:06:17 2019 +0000
tree 0cd8c23c6293498256471555a3a8da0d9ed7334d
parent 31d00d80a21ffbc5bc03c7b90de030b29660a3bd

[MIPS GlobalISel] Lower call for callee that is register

Lower call for callee that is register for MIPS32.
Register should contain callee function address.

Differential Revision: https://reviews.llvm.org/D62585

llvm-svn: 362204

llvm/lib/Target/Mips/MipsCallLowering.cpp

diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp
index 0cee6e7..04aff60 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -522,12 +522,8 @@
   MachineInstrBuilder CallSeqStart =
       MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
 
-  // FIXME: Add support for pic calling sequences, long call sequences for O32,
-  //       N32 and N64. First handle the case when Callee.isReg().
-  if (Callee.isReg())
-    return false;
-
-  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Mips::JAL);
+  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
+      Callee.isReg() ? Mips::JALRPseudo : Mips::JAL);
   MIB.addDef(Mips::SP, RegState::Implicit);
   MIB.add(Callee);
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
@@ -573,6 +569,12 @@
   CallSeqStart.addImm(NextStackOffset).addImm(0);
 
   MIRBuilder.insertInstr(MIB);
+  if (MIB->getOpcode() == Mips::JALRPseudo) {
+    const MipsSubtarget &STI =
+        static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
+    MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
+                         *STI.getRegBankInfo());
+  }
 
   if (OrigRet.Reg) {