Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
Add an extra run with -regalloc=basic to keep them honest.
llvm-svn: 128654
diff --git a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
index 50b43b4..6601d25 100644
--- a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips2 < %s -regalloc=basic | FileCheck %s
; All test functions do the same thing - they return the first variable
@@ -56,14 +57,14 @@
; CHECK: va2:
; CHECK: addiu $sp, $sp, -40
-; CHECK: addiu $2, $sp, 44
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
; CHECK: sw $5, 44($sp)
; CHECK: sw $6, 48($sp)
; CHECK: sw $7, 52($sp)
-; CHECK: addiu $3, $2, 7
-; CHECK: addiu $5, $zero, -8
-; CHECK: and $3, $3, $5
-; CHECK: ldc1 $f0, 0($3)
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
@@ -109,11 +110,11 @@
; CHECK: addiu $sp, $sp, -48
; CHECK: sw $6, 56($sp)
; CHECK: sw $7, 60($sp)
-; CHECK: addiu $3, $sp, 56
-; CHECK: addiu $6, $3, 7
-; CHECK: addiu $7, $zero, -8
-; CHECK: and $2, $6, $7
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 56
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
@@ -165,11 +166,11 @@
; CHECK: va6:
; CHECK: addiu $sp, $sp, -48
; CHECK: sw $7, 60($sp)
-; CHECK: addiu $2, $sp, 60
-; CHECK: addiu $3, $2, 7
-; CHECK: addiu $4, $zero, -8
-; CHECK: and $3, $3, $4
-; CHECK: ldc1 $f0, 0($3)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 60
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
@@ -215,11 +216,11 @@
; CHECK: va8:
; CHECK: addiu $sp, $sp, -48
-; CHECK: addiu $3, $sp, 64
-; CHECK: addiu $4, $3, 7
-; CHECK: addiu $5, $zero, -8
-; CHECK: and $2, $4, $5
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
@@ -269,9 +270,9 @@
; CHECK: va10:
; CHECK: addiu $sp, $sp, -56
-; CHECK: addiu $3, $sp, 76
-; CHECK: addiu $2, $3, 7
-; CHECK: addiu $4, $zero, -8
-; CHECK: and $2, $2, $4
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 76
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}