commit f4d3113a5fd6ac09dc5498bbbdfecc7d8e336951
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Aug 06 03:59:31 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Aug 06 03:59:31 2019 +0000
tree 270e8cd714097bf8bfb5a449750eca9348934751
parent acd0a53c02bcad5748dcac9ae25842ea5d564341

CodeGen: Migration to using Register

llvm-svn: 367974

llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
index 2552e91..48d19c0 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
@@ -1141,14 +1141,14 @@
     return true;
   }
 
-  unsigned Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
+  Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
                                         In, I->getOperand(0)->hasOneUse());
   if (!Reg)
     return false;
   MachineBasicBlock::iterator Iter = FuncInfo.InsertPt;
   --Iter;
   assert(Iter->isBitcast());
-  Iter->setPhysRegsDeadExcept(ArrayRef<unsigned>(), TRI);
+  Iter->setPhysRegsDeadExcept(ArrayRef<Register>(), TRI);
   updateValueMap(I, Reg);
   return true;
 }