ScheduleDAGInstrs: In functions with tail calls PseudoSourceValues are not non-aliasing distinct objects
The code that builds the dependence graph assumes that two PseudoSourceValues
don't alias. In a tail calling function two FixedStackObjects might refer to the
same location. Worse 'immutable' fixed stack objects like function arguments are
not immutable and will be clobbered.
Change this so that a load from a FixedStackObject is not invariant in a tail
calling function and don't return a PseudoSourceValue for an instruction in tail
calling functions when building the dependence graph so that we handle function
arguments conservatively.
Fix for PR23459.
rdar://20740035
llvm-svn: 236916
diff --git a/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll b/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll
new file mode 100644
index 0000000..57f9687
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll
@@ -0,0 +1,42 @@
+; RUN: llc -mcpu=cyclone -debug-only=misched < %s 2>&1 | FileCheck %s
+
+; REQUIRE: asserts
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios7.0.0"
+
+define void @caller2(i8* %a0, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9) {
+entry:
+ tail call void @callee2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a0)
+ ret void
+}
+
+declare void @callee2(i8*, i8*, i8*, i8*, i8*,
+ i8*, i8*, i8*, i8*, i8*)
+
+; Make sure there is a dependence between the load and store to the same stack
+; location during a tail call. Tail calls clobber the incoming argument area and
+; therefore it is not safe to assume argument locations are invariant.
+; PR23459 has a test case that we where miscompiling because of this at the
+; time.
+
+; CHECK: Frame Objects
+; CHECK: fi#-4: {{.*}} fixed, at location [SP+8]
+; CHECK: fi#-3: {{.*}} fixed, at location [SP]
+; CHECK: fi#-2: {{.*}} fixed, at location [SP+8]
+; CHECK: fi#-1: {{.*}} fixed, at location [SP]
+
+; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
+; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
+; CHECK: STRXui %vreg{{.*}}, <fi#-4>
+; CHECK: STRXui [[VRB]], <fi#-3>
+
+; Make sure that there is an dependence edge between fi#-2 and fi#-4.
+; Without this edge the scheduler would be free to move the store accross the load.
+
+; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2>
+; CHECK-NOT: SU
+; CHECK: Successors:
+; CHECK: ch SU([[DEPSTORE:.*]]): Latency=0
+
+; CHECK: SU([[DEPSTORE]]): STRXui %vreg0, <fi#-4>
diff --git a/llvm/test/CodeGen/ARM/debug-frame.ll b/llvm/test/CodeGen/ARM/debug-frame.ll
index f7caaea..1348292 100644
--- a/llvm/test/CodeGen/ARM/debug-frame.ll
+++ b/llvm/test/CodeGen/ARM/debug-frame.ll
@@ -179,7 +179,7 @@
; CHECK-FP: .cfi_offset r4, -36
; CHECK-FP: add r11, sp, #28
; CHECK-FP: .cfi_def_cfa r11, 8
-; CHECK-FP: sub sp, sp, #28
+; CHECK-FP: sub sp, sp, #44
; CHECK-FP: .cfi_endproc
; CHECK-FP-ELIM-LABEL: _Z4testiiiiiddddd:
@@ -195,8 +195,8 @@
; CHECK-FP-ELIM: .cfi_offset r6, -28
; CHECK-FP-ELIM: .cfi_offset r5, -32
; CHECK-FP-ELIM: .cfi_offset r4, -36
-; CHECK-FP-ELIM: sub sp, sp, #28
-; CHECK-FP-ELIM: .cfi_def_cfa_offset 64
+; CHECK-FP-ELIM: sub sp, sp, #36
+; CHECK-FP-ELIM: .cfi_def_cfa_offset 72
; CHECK-FP-ELIM: .cfi_endproc
; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd:
diff --git a/llvm/test/CodeGen/ARM/ehabi.ll b/llvm/test/CodeGen/ARM/ehabi.ll
index ebf0c2a..088e48d 100644
--- a/llvm/test/CodeGen/ARM/ehabi.ll
+++ b/llvm/test/CodeGen/ARM/ehabi.ll
@@ -146,8 +146,8 @@
; CHECK-FP: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-FP: .setfp r11, sp, #28
; CHECK-FP: add r11, sp, #28
-; CHECK-FP: .pad #28
-; CHECK-FP: sub sp, sp, #28
+; CHECK-FP: .pad #44
+; CHECK-FP: sub sp, sp, #44
; CHECK-FP: .personality __gxx_personality_v0
; CHECK-FP: .handlerdata
; CHECK-FP: .fnend
@@ -156,8 +156,8 @@
; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-FP-ELIM: .pad #28
-; CHECK-FP-ELIM: sub sp, sp, #28
+; CHECK-FP-ELIM: .pad #36
+; CHECK-FP-ELIM: sub sp, sp, #36
; CHECK-FP-ELIM: .personality __gxx_personality_v0
; CHECK-FP-ELIM: .handlerdata
; CHECK-FP-ELIM: .fnend
@@ -205,7 +205,7 @@
; DWARF-FP: .cfi_offset r4, -36
; DWARF-FP: add r11, sp, #28
; DWARF-FP: .cfi_def_cfa r11, 8
-; DWARF-FP: sub sp, sp, #28
+; DWARF-FP: sub sp, sp, #44
; DWARF-FP: sub sp, r11, #28
; DWARF-FP: pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; DWARF-FP: mov pc, lr
@@ -226,9 +226,9 @@
; DWARF-FP-ELIM: .cfi_offset r6, -28
; DWARF-FP-ELIM: .cfi_offset r5, -32
; DWARF-FP-ELIM: .cfi_offset r4, -36
-; DWARF-FP-ELIM: sub sp, sp, #28
-; DWARF-FP-ELIM: .cfi_def_cfa_offset 64
-; DWARF-FP-ELIM: add sp, sp, #28
+; DWARF-FP-ELIM: sub sp, sp, #36
+; DWARF-FP-ELIM: .cfi_def_cfa_offset 72
+; DWARF-FP-ELIM: add sp, sp, #36
; DWARF-FP-ELIM: pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; DWARF-FP-ELIM: mov pc, lr
; DWARF-FP-ELIM: .cfi_endproc
diff --git a/llvm/test/CodeGen/X86/tailcallstack64.ll b/llvm/test/CodeGen/X86/tailcallstack64.ll
index bff5f99..158b777 100644
--- a/llvm/test/CodeGen/X86/tailcallstack64.ll
+++ b/llvm/test/CodeGen/X86/tailcallstack64.ll
@@ -12,9 +12,9 @@
; Add %in1 %p1 to a different temporary register (%eax).
; CHECK: addl {{%edi|%ecx}}, [[R1]]
; Move param %in2 to stack.
-; CHECK: movl [[R2]], [[A1]](%rsp)
+; CHECK-DAG: movl [[R2]], [[A1]](%rsp)
; Move result of addition to stack.
-; CHECK: movl [[R1]], [[A2]](%rsp)
+; CHECK-DAG: movl [[R1]], [[A2]](%rsp)
; Eventually, do a TAILCALL
; CHECK: TAILCALL