commit f56a6d84b6b7c3432db6c2ed7280d3dbe3cb4f3d
author Matthias Braun <matze@braunis.de> Fri May 26 01:29:32 2017 +0000
committer Matthias Braun <matze@braunis.de> Fri May 26 01:29:32 2017 +0000
tree c32e2e0d401b5aebae863d6e79a758d531d4f280
parent 9e6826de773f7dbd16f068d884342acbbeade3cd

Revert "LivePhysRegs: Skip reserved regs in computeLiveIns; NFCI"

Tentatively revert, suspecting that it caused breakage in stage2
buildbots.

This reverts commit r303949.
This reverts commit r303937.

llvm-svn: 303955

llvm/lib/CodeGen/BranchFolding.cpp

diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index 03ceac1..025b9fc 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -153,14 +153,13 @@
 
   TriedMerging.clear();
 
-  MachineRegisterInfo &MRI = MF.getRegInfo();
   AfterBlockPlacement = AfterPlacement;
   TII = tii;
   TRI = tri;
   MMI = mmi;
   MLI = mli;
-  this->MRI = &MRI;
 
+  MachineRegisterInfo &MRI = MF.getRegInfo();
   UpdateLiveIns = MRI.tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF);
   if (!UpdateLiveIns)
     MRI.invalidateLiveness();
@@ -352,7 +351,7 @@
 
   if (UpdateLiveIns) {
     NewDest->clearLiveIns();
-    computeLiveIns(LiveRegs, *MRI, *NewDest);
+    computeLiveIns(LiveRegs, *TRI, *NewDest);
   }
 
   ++NumTailMerge;
@@ -389,7 +388,7 @@
   MBBFreqInfo.setBlockFreq(NewMBB, MBBFreqInfo.getBlockFreq(&CurMBB));
 
   if (UpdateLiveIns)
-    computeLiveIns(LiveRegs, *MRI, *NewMBB);
+    computeLiveIns(LiveRegs, *TRI, *NewMBB);
 
   // Add the new block to the funclet.
   const auto &FuncletI = FuncletMembership.find(&CurMBB);

llvm/lib/CodeGen/BranchFolding.h

diff --git a/llvm/lib/CodeGen/BranchFolding.h b/llvm/lib/CodeGen/BranchFolding.h
index 9268113..4852721 100644
--- a/llvm/lib/CodeGen/BranchFolding.h
+++ b/llvm/lib/CodeGen/BranchFolding.h
@@ -108,7 +108,6 @@
     bool UpdateLiveIns;
     unsigned MinCommonTailLength;
     const TargetInstrInfo *TII;
-    const MachineRegisterInfo *MRI;
     const TargetRegisterInfo *TRI;
     MachineModuleInfo *MMI;
     MachineLoopInfo *MLI;

llvm/lib/CodeGen/BranchRelaxation.cpp

diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp
index feaabb4..7af1369 100644
--- a/llvm/lib/CodeGen/BranchRelaxation.cpp
+++ b/llvm/lib/CodeGen/BranchRelaxation.cpp
@@ -259,7 +259,7 @@
 
   // Need to fix live-in lists if we track liveness.
   if (TRI->trackLivenessAfterRegAlloc(*MF))
-    computeLiveIns(LiveRegs, MF->getRegInfo(), *NewBB);
+    computeLiveIns(LiveRegs, *TRI, *NewBB);
 
   ++NumSplit;
 

llvm/lib/CodeGen/LivePhysRegs.cpp

diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp
index 774fa4c..d90e893 100644
--- a/llvm/lib/CodeGen/LivePhysRegs.cpp
+++ b/llvm/lib/CodeGen/LivePhysRegs.cpp
@@ -214,10 +214,8 @@
   addBlockLiveIns(MBB);
 }
 
-void llvm::computeLiveIns(LivePhysRegs &LiveRegs,
-                          const MachineRegisterInfo &MRI,
+void llvm::computeLiveIns(LivePhysRegs &LiveRegs, const TargetRegisterInfo &TRI,
                           MachineBasicBlock &MBB) {
-  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
   assert(MBB.livein_empty());
   LiveRegs.init(TRI);
   LiveRegs.addLiveOutsNoPristines(MBB);
@@ -225,12 +223,10 @@
     LiveRegs.stepBackward(MI);
 
   for (unsigned Reg : LiveRegs) {
-    if (MRI.isReserved(Reg))
-      continue;
     // Skip the register if we are about to add one of its super registers.
     bool ContainsSuperReg = false;
     for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) {
-      if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
+      if (LiveRegs.contains(*SReg)) {
         ContainsSuperReg = true;
         break;
       }