AMDGPU: Match some med3 patterns
llvm-svn: 259089
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3.ll b/llvm/test/CodeGen/AMDGPU/fmed3.ll
new file mode 100644
index 0000000..c02c084
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fmed3.ll
@@ -0,0 +1,131 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN %s
+
+declare i32 @llvm.r600.read.tidig.x() #0
+declare float @llvm.minnum.f32(float, float) #0
+declare float @llvm.maxnum.f32(float, float) #0
+declare double @llvm.minnum.f64(double, double) #0
+declare double @llvm.maxnum.f64(double, double) #0
+
+; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_f32:
+; NOSNAN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0
+
+; SNAN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
+; SNAN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
+define void @v_test_fmed3_r_i_i_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
+ %a = load float, float addrspace(1)* %gep0
+
+ %max = call float @llvm.maxnum.f32(float %a, float 2.0)
+ %med = call float @llvm.minnum.f32(float %max, float 4.0)
+
+ store float %med, float addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_commute0_f32:
+; NOSNAN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0
+
+; SNAN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
+; SNAN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
+define void @v_test_fmed3_r_i_i_commute0_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
+ %a = load float, float addrspace(1)* %gep0
+
+ %max = call float @llvm.maxnum.f32(float 2.0, float %a)
+ %med = call float @llvm.minnum.f32(float 4.0, float %max)
+
+ store float %med, float addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_commute1_f32:
+; NOSNAN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0
+
+; SNAN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
+; SNAN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
+define void @v_test_fmed3_r_i_i_commute1_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
+ %a = load float, float addrspace(1)* %gep0
+
+ %max = call float @llvm.maxnum.f32(float %a, float 2.0)
+ %med = call float @llvm.minnum.f32(float 4.0, float %max)
+
+ store float %med, float addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_constant_order_f32:
+; GCN: v_max_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
+; GCN: v_min_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
+define void @v_test_fmed3_r_i_i_constant_order_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
+ %a = load float, float addrspace(1)* %gep0
+
+ %max = call float @llvm.maxnum.f32(float %a, float 4.0)
+ %med = call float @llvm.minnum.f32(float %max, float 2.0)
+
+ store float %med, float addrspace(1)* %outgep
+ ret void
+}
+
+
+; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_multi_use_f32:
+; GCN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
+; GCN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
+define void @v_test_fmed3_r_i_i_multi_use_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
+ %a = load float, float addrspace(1)* %gep0
+
+ %max = call float @llvm.maxnum.f32(float %a, float 2.0)
+ %med = call float @llvm.minnum.f32(float %max, float 4.0)
+
+ store volatile float %med, float addrspace(1)* %outgep
+ store volatile float %max, float addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_f64:
+; GCN: v_max_f64 {{v\[[0-9]+:[0-9]+\]}}, 2.0, {{v\[[0-9]+:[0-9]+\]}}
+; GCN: v_min_f64 {{v\[[0-9]+:[0-9]+\]}}, 4.0, {{v\[[0-9]+:[0-9]+\]}}
+define void @v_test_fmed3_r_i_i_f64(double addrspace(1)* %out, double addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr double, double addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr double, double addrspace(1)* %out, i32 %tid
+ %a = load double, double addrspace(1)* %gep0
+
+ %max = call double @llvm.maxnum.f64(double %a, double 2.0)
+ %med = call double @llvm.minnum.f64(double %max, double 4.0)
+
+ store double %med, double addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_no_nans_f32:
+; GCN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0
+define void @v_test_fmed3_r_i_i_no_nans_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #2 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
+ %a = load float, float addrspace(1)* %gep0
+
+ %max = call float @llvm.maxnum.f32(float %a, float 2.0)
+ %med = call float @llvm.minnum.f32(float %max, float 4.0)
+
+ store float %med, float addrspace(1)* %outgep
+ ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="false" }
+attributes #2 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="true" }
diff --git a/llvm/test/CodeGen/AMDGPU/smed3.ll b/llvm/test/CodeGen/AMDGPU/smed3.ll
new file mode 100644
index 0000000..18c8c2c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/smed3.ll
@@ -0,0 +1,120 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+declare i32 @llvm.r600.read.tidig.x() #0
+
+; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i32:
+; GCN: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
+define void @v_test_smed3_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+ %a = load i32, i32 addrspace(1)* %gep0
+
+ %icmp0 = icmp sgt i32 %a, 12
+ %i0 = select i1 %icmp0, i32 %a, i32 12
+
+ %icmp1 = icmp slt i32 %i0, 17
+ %i1 = select i1 %icmp1, i32 %i0, i32 17
+
+ store i32 %i1, i32 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_smed3_multi_use_r_i_i_i32:
+; GCN: v_max_i32
+; GCN: v_min_i32
+define void @v_test_smed3_multi_use_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+ %a = load i32, i32 addrspace(1)* %gep0
+
+ %icmp0 = icmp sgt i32 %a, 12
+ %i0 = select i1 %icmp0, i32 %a, i32 12
+
+ %icmp1 = icmp slt i32 %i0, 17
+ %i1 = select i1 %icmp1, i32 %i0, i32 17
+
+ store volatile i32 %i0, i32 addrspace(1)* %outgep
+ store volatile i32 %i1, i32 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_smed3_r_i_i_constant_order_i32:
+; GCN: v_max_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
+; GCN: v_min_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
+define void @v_test_smed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+ %a = load i32, i32 addrspace(1)* %gep0
+
+ %icmp0 = icmp sgt i32 %a, 17
+ %i0 = select i1 %icmp0, i32 %a, i32 17
+
+ %icmp1 = icmp slt i32 %i0, 12
+ %i1 = select i1 %icmp1, i32 %i0, i32 12
+
+ store i32 %i1, i32 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_smed3_r_i_i_sign_mismatch_i32:
+; GCN: v_max_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
+; GCN: v_min_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
+define void @v_test_smed3_r_i_i_sign_mismatch_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+ %a = load i32, i32 addrspace(1)* %gep0
+
+ %icmp0 = icmp ugt i32 %a, 12
+ %i0 = select i1 %icmp0, i32 %a, i32 12
+
+ %icmp1 = icmp slt i32 %i0, 17
+ %i1 = select i1 %icmp1, i32 %i0, i32 17
+
+ store i32 %i1, i32 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i64:
+; GCN: v_cmp_lt_i64
+; GCN: v_cmp_gt_i64
+define void @v_test_smed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+ %a = load i64, i64 addrspace(1)* %gep0
+
+ %icmp0 = icmp sgt i64 %a, 12
+ %i0 = select i1 %icmp0, i64 %a, i64 12
+
+ %icmp1 = icmp slt i64 %i0, 17
+ %i1 = select i1 %icmp1, i64 %i0, i64 17
+
+ store i64 %i1, i64 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i16:
+; GCN: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
+define void @v_test_smed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
+ %a = load i16, i16 addrspace(1)* %gep0
+
+ %icmp0 = icmp sgt i16 %a, 12
+ %i0 = select i1 %icmp0, i16 %a, i16 12
+
+ %icmp1 = icmp slt i16 %i0, 17
+ %i1 = select i1 %icmp1, i16 %i0, i16 17
+
+ store i16 %i1, i16 addrspace(1)* %outgep
+ ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/umed3.ll b/llvm/test/CodeGen/AMDGPU/umed3.ll
new file mode 100644
index 0000000..3cdd5ce
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/umed3.ll
@@ -0,0 +1,119 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+declare i32 @llvm.r600.read.tidig.x() #0
+
+; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i32:
+; GCN: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
+define void @v_test_umed3_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+ %a = load i32, i32 addrspace(1)* %gep0
+
+ %icmp0 = icmp ugt i32 %a, 12
+ %i0 = select i1 %icmp0, i32 %a, i32 12
+
+ %icmp1 = icmp ult i32 %i0, 17
+ %i1 = select i1 %icmp1, i32 %i0, i32 17
+
+ store i32 %i1, i32 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umed3_multi_use_r_i_i_i32:
+; GCN: v_max_u32
+; GCN: v_min_u32
+define void @v_test_umed3_multi_use_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+ %a = load i32, i32 addrspace(1)* %gep0
+
+ %icmp0 = icmp ugt i32 %a, 12
+ %i0 = select i1 %icmp0, i32 %a, i32 12
+
+ %icmp1 = icmp ult i32 %i0, 17
+ %i1 = select i1 %icmp1, i32 %i0, i32 17
+
+ store volatile i32 %i0, i32 addrspace(1)* %outgep
+ store volatile i32 %i1, i32 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umed3_r_i_i_constant_order_i32:
+; GCN: v_max_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
+; GCN: v_min_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
+define void @v_test_umed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+ %a = load i32, i32 addrspace(1)* %gep0
+
+ %icmp0 = icmp ugt i32 %a, 17
+ %i0 = select i1 %icmp0, i32 %a, i32 17
+
+ %icmp1 = icmp ult i32 %i0, 12
+ %i1 = select i1 %icmp1, i32 %i0, i32 12
+
+ store i32 %i1, i32 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umed3_r_i_i_sign_mismatch_i32:
+; GCN: v_max_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
+; GCN: v_min_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
+define void @v_test_umed3_r_i_i_sign_mismatch_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
+ %a = load i32, i32 addrspace(1)* %gep0
+
+ %icmp0 = icmp sgt i32 %a, 12
+ %i0 = select i1 %icmp0, i32 %a, i32 12
+
+ %icmp1 = icmp ult i32 %i0, 17
+ %i1 = select i1 %icmp1, i32 %i0, i32 17
+
+ store i32 %i1, i32 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i64:
+; GCN: v_cmp_lt_u64
+; GCN: v_cmp_gt_u64
+define void @v_test_umed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+ %a = load i64, i64 addrspace(1)* %gep0
+
+ %icmp0 = icmp ugt i64 %a, 12
+ %i0 = select i1 %icmp0, i64 %a, i64 12
+
+ %icmp1 = icmp ult i64 %i0, 17
+ %i1 = select i1 %icmp1, i64 %i0, i64 17
+
+ store i64 %i1, i64 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i16:
+; GCN: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
+define void @v_test_umed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 {
+ %tid = call i32 @llvm.r600.read.tidig.x()
+ %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
+ %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
+ %a = load i16, i16 addrspace(1)* %gep0
+
+ %icmp0 = icmp ugt i16 %a, 12
+ %i0 = select i1 %icmp0, i16 %a, i16 12
+
+ %icmp1 = icmp ult i16 %i0, 17
+ %i1 = select i1 %icmp1, i16 %i0, i16 17
+
+ store i16 %i1, i16 addrspace(1)* %outgep
+ ret void
+}
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }