commit f6e7e12f752b7366240b473df1da151f7697a794
author Craig Topper <craig.topper@gmail.com> Tue Mar 27 07:21:54 2012 +0000
committer Craig Topper <craig.topper@gmail.com> Tue Mar 27 07:21:54 2012 +0000
tree dff3ef3a6184cccf1f2165f833b71ed87e99add2
parent 8a7633c74e4ef3a4206f280210cc3a543dafd8d9

Remove unnecessary llvm:: qualifications

llvm-svn: 153500

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 4445dcd..e378a9c 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -1330,8 +1330,8 @@
   // LDM/STM:
   //   {15-0}  = Bitfield of GPRs.
   unsigned Reg = MI.getOperand(Op).getReg();
-  bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
-  bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
+  bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
+  bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
 
   unsigned Binary = 0;