[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential review.
llvm-svn: 314073
diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
new file mode 100644
index 0000000..04381c5
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
@@ -0,0 +1,130 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_ilesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r5, r4, 63
+; CHECK-NEXT: rldicl r6, r3, 1, 63
+; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: adde r3, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r5, r4, 63
+; CHECK-NEXT: rldicl r6, r3, 1, 63
+; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: adde r3, r5, r6
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+define signext i32 @test_ilesll_z(i64 %a) {
+; CHECK-LABEL: test_ilesll_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addi r4, r3, -1
+; CHECK-NEXT: or r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+define signext i32 @test_ilesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_ilesll_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addi r4, r3, -1
+; CHECK-NEXT: or r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+define void @test_ilesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sradi r6, r4, 63
+; CHECK: subfc r4, r3, r4
+; CHECK: rldicl r3, r3, 1, 63
+; CHECK: adde r3, r6, r3
+; CHECK: std r3,
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_ilesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sradi r6, r4, 63
+; CHECK-DAG: rldicl r3, r3, 1, 63
+; CHECK-DAG: subfc r4, r3, r4
+; CHECK: adde r3, r6, r3
+; CHECK: neg r3, r3
+; CHECK: std r3,
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_ilesll_z_store(i64 %a) {
+; CHECK-LABEL: test_ilesll_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: addi r5, r3, -1
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: or r3, r5, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_ilesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_ilesll_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: addi r5, r3, -1
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: or r3, r5, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}