commit f8a841b88e2e73407258ad508e0a8bac41573f7f
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jun 24 16:24:03 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jun 24 16:24:03 2019 +0000
tree 8b62987363a6d3d06ccc98282dc6bc0ca9f6871f
parent 9f4c7e8170cae9d243b99cdecc6b05d214b0427d

AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1

Try to fail for scc, since I don't think that should ever be produced.

llvm-svn: 364199

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 6484b7d..590fd25 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -232,12 +232,17 @@
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
   const MachineOperand &MO = I.getOperand(0);
-  const TargetRegisterClass *RC =
-      TRI.getConstrainedRegClassForOperand(MO, MRI);
-  if (RC)
-    RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
-  I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
-  return true;
+
+  // FIXME: Interface for getConstrainedRegClassForOperand needs work. The
+  // regbank check here is to know why getConstrainedRegClassForOperand failed.
+  const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, MRI);
+  if ((!RC && !MRI.getRegBankOrNull(MO.getReg())) ||
+      (RC && RBI.constrainGenericRegister(MO.getReg(), *RC, MRI))) {
+    I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
+    return true;
+  }
+
+  return false;
 }
 
 bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 0caeb81..fe675b5 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1688,10 +1688,23 @@
 
   Size = PowerOf2Ceil(Size);
   switch (Size) {
-  case 1:
-    if (RB->getID() == AMDGPU::SCCRegBankID)
+  case 1: {
+    switch (RB->getID()) {
+    case AMDGPU::VGPRRegBankID:
+      return &AMDGPU::VGPR_32RegClass;
+    case AMDGPU::VCCRegBankID:
+      // TODO: Check wavesize
+      return &AMDGPU::SReg_64_XEXECRegClass;
+    case AMDGPU::SGPRRegBankID:
       return &AMDGPU::SReg_32_XM0RegClass;
-    break;
+    case AMDGPU::SCCRegBankID:
+      // This needs to return an allocatable class, so don't bother returning
+      // the dummy SCC class.
+      return &AMDGPU::SReg_32_XM0RegClass;
+    default:
+      llvm_unreachable("unknown register bank");
+    }
+  }
   case 32:
     return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
                                                   &AMDGPU::SReg_32_XM0RegClass;