diff --git a/lldb/source/Host/common/NativeProcessProtocol.cpp b/lldb/source/Host/common/NativeProcessProtocol.cpp
index 7ccf846..f2f721f 100644
--- a/lldb/source/Host/common/NativeProcessProtocol.cpp
+++ b/lldb/source/Host/common/NativeProcessProtocol.cpp
@@ -372,6 +372,43 @@
       });
 }
 
+llvm::Expected<llvm::ArrayRef<uint8_t>>
+NativeProcessProtocol::GetSoftwareBreakpointTrapOpcode(size_t size_hint) {
+  static const uint8_t g_aarch64_opcode[] = {0x00, 0x00, 0x20, 0xd4};
+  static const uint8_t g_i386_opcode[] = {0xCC};
+  static const uint8_t g_mips64_opcode[] = {0x00, 0x00, 0x00, 0x0d};
+  static const uint8_t g_mips64el_opcode[] = {0x0d, 0x00, 0x00, 0x00};
+  static const uint8_t g_s390x_opcode[] = {0x00, 0x01};
+  static const uint8_t g_ppc64le_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
+
+  switch (GetArchitecture().GetMachine()) {
+  case llvm::Triple::aarch64:
+    return g_aarch64_opcode;
+
+  case llvm::Triple::x86:
+  case llvm::Triple::x86_64:
+    return g_i386_opcode;
+
+  case llvm::Triple::mips:
+  case llvm::Triple::mips64:
+    return g_mips64_opcode;
+
+  case llvm::Triple::mipsel:
+  case llvm::Triple::mips64el:
+    return g_mips64el_opcode;;
+
+  case llvm::Triple::systemz:
+    return g_s390x_opcode;
+
+  case llvm::Triple::ppc64le:
+    return g_ppc64le_opcode;
+
+  default:
+    return llvm::createStringError(llvm::inconvertibleErrorCode(),
+                                   "CPU type not supported!");
+  }
+}
+
 Status NativeProcessProtocol::RemoveBreakpoint(lldb::addr_t addr,
                                                bool hardware) {
   if (hardware)