[MachineOperand][Target] MachineOperand::isRenamable semantics changes
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers. This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.
Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).
Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.
Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.
Clear the IsRenamable bit when changing an operand's register value.
Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.
Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.
Reviewers: qcolombet, MatzeB
Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D43042
llvm-svn: 325931
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 7e510a1..e99842b 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -538,4 +538,5 @@
let InstructionSet = AArch64InstrInfo;
let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
+ let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index c7b3b6d..d799218 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -686,6 +686,7 @@
SDWA9AsmParserVariant,
DPPAsmParserVariant];
let AssemblyWriters = [AMDGPUAsmWriter];
+ let AllowRegisterRenaming = 1;
}
// Dummy Instruction itineraries for pseudo instructions
diff --git a/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp b/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp
index bc8cf5e..331b17b 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp
@@ -278,11 +278,6 @@
.add(MI.getOperand(0))
.addImm(0); // omod
}
- // Clear isRenamable bit if new opcode requires it to be 0.
- if (NewMI->hasExtraSrcRegAllocReq())
- for (MachineOperand &NewMO : NewMI->uses())
- if (NewMO.isReg() && NewMO.isUse())
- NewMO.setIsRenamable(false);
break;
}
case AMDGPU::SI_KILL_I1_TERMINATOR: {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index 9e7aea6..5fbee37 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -186,6 +186,9 @@
let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
let AsmVariantName = AMDGPUAsmVariants.Default;
+
+ // Avoid changing source registers in a way that violates constant bus read limitations.
+ let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0))))));
}
class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
@@ -203,8 +206,6 @@
: PseudoInstSI<outs, ins, pattern, asm> {
let VALU = 1;
let Uses = [EXEC];
- // Avoid changing source registers in a way that violates constant bus read limitations.
- let hasExtraSrcRegAllocReq = 1;
}
class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
index e77c98a..2dc6f27 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -246,7 +246,6 @@
DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst);
PrepareExecInst->getOperand(0).setReg(AMDGPU::EXEC);
- PrepareExecInst->getOperand(0).setIsRenamable(false);
DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n');
@@ -353,8 +352,7 @@
for (MachineInstr *OtherInst : OtherUseInsts) {
OtherInst->substituteRegister(CopyToExec, AMDGPU::EXEC,
- AMDGPU::NoSubRegister, *TRI,
- /*ClearIsRenamable=*/true);
+ AMDGPU::NoSubRegister, *TRI);
}
}
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index dfe18de..520d5dd 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -81,8 +81,6 @@
let UseNamedOperandTable = 1;
let VOP3_OPSEL = isVop3OpSel;
let IsPacked = P.IsPacked;
- // Avoid changing source registers in a way that violates constant bus read limitations.
- let hasExtraSrcRegAllocReq = 1;
string Mnemonic = opName;
string AsmOperands = !if(isVop3OpSel,
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 705cfe0..ecb2ef2 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -1043,4 +1043,5 @@
let AssemblyWriters = [ARMAsmWriter];
let AssemblyParsers = [ARMAsmParser];
let AssemblyParserVariants = [ARMAsmParserVariant];
+ let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 03fbd77..d299024 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1378,7 +1378,6 @@
MachineInstrBuilder LDM, STM;
if (isThumb1 || !MI->getOperand(1).isDead()) {
MachineOperand LDWb(MI->getOperand(1));
- LDWb.setIsRenamable(false);
LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
: isThumb1 ? ARM::tLDMIA_UPD
: ARM::LDMIA_UPD))
@@ -1389,7 +1388,6 @@
if (isThumb1 || !MI->getOperand(0).isDead()) {
MachineOperand STWb(MI->getOperand(0));
- STWb.setIsRenamable(false);
STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
: isThumb1 ? ARM::tSTMIA_UPD
: ARM::STMIA_UPD))
@@ -1399,11 +1397,9 @@
}
MachineOperand LDBase(MI->getOperand(3));
- LDBase.setIsRenamable(false);
LDM.add(LDBase).add(predOps(ARMCC::AL));
MachineOperand STBase(MI->getOperand(2));
- STBase.setIsRenamable(false);
STM.add(STBase).add(predOps(ARMCC::AL));
// Sort the scratch registers into ascending order.
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index b14b2c6..9e6bfbc 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -608,7 +608,6 @@
MIB.add(MI.getOperand(OpIdx++));
if (IsExt) {
MachineOperand VdSrc(MI.getOperand(OpIdx++));
- VdSrc.setIsRenamable(false);
MIB.add(VdSrc);
}
@@ -620,7 +619,6 @@
// Copy the other source register operand.
MachineOperand VmSrc(MI.getOperand(OpIdx++));
- VmSrc.setIsRenamable(false);
MIB.add(VmSrc);
// Copy the predicate operands.
@@ -1470,7 +1468,6 @@
// Copy the destination register.
MachineOperand Dst(MI.getOperand(OpIdx++));
- Dst.setIsRenamable(false);
MIB.add(Dst);
// Copy the predicate operands.
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 19afaed..c5629b9 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -9196,8 +9196,6 @@
// Thumb1 post-indexed loads are really just single-register LDMs.
case ARM::tLDR_postidx: {
MachineOperand Def(MI.getOperand(1));
- if (TargetRegisterInfo::isPhysicalRegister(Def.getReg()))
- Def.setIsRenamable(false);
BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD))
.add(Def) // Rn_wb
.add(MI.getOperand(2)) // Rn
diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td
index 169704c..e1f3dec 100644
--- a/llvm/lib/Target/Hexagon/Hexagon.td
+++ b/llvm/lib/Target/Hexagon/Hexagon.td
@@ -359,4 +359,5 @@
let AssemblyParsers = [HexagonAsmParser];
let AssemblyParserVariants = [HexagonAsmParserVariant];
let AssemblyWriters = [HexagonAsmWriter];
+ let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/Hexagon/RDFCopy.cpp b/llvm/lib/Target/Hexagon/RDFCopy.cpp
index 212f75c..4339fa2 100644
--- a/llvm/lib/Target/Hexagon/RDFCopy.cpp
+++ b/llvm/lib/Target/Hexagon/RDFCopy.cpp
@@ -101,7 +101,6 @@
bool CopyPropagation::run() {
scanBlock(&DFG.getMF().front());
- MachineRegisterInfo &MRI = DFG.getMF().getRegInfo();
if (trace()) {
dbgs() << "Copies:\n";
@@ -181,8 +180,6 @@
unsigned NewReg = MinPhysReg(SR);
Op.setReg(NewReg);
Op.setSubReg(0);
- if (MRI.isReserved(NewReg))
- Op.setIsRenamable(false);
DFG.unlinkUse(UA, false);
if (AtCopy != 0) {
UA.Addr->linkToDef(UA.Id, DFG.addr<DefNode*>(AtCopy));
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index f8e7394..4a99a9f 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,4 +242,5 @@
let InstructionSet = MipsInstrInfo;
let AssemblyParsers = [MipsAsmParser];
let AssemblyParserVariants = [MipsAsmParserVariant];
+ let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 4650220..24abe7a 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -465,4 +465,5 @@
let AssemblyParsers = [PPCAsmParser];
let AssemblyParserVariants = [PPCAsmParserVariant];
+ let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 4caaaa4..3e80d74 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -92,4 +92,5 @@
let InstructionSet = RISCVInstrInfo;
let AssemblyParsers = [RISCVAsmParser];
let AssemblyWriters = [RISCVAsmWriter];
+ let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 9e0a297..dbe763f 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -176,4 +176,5 @@
let InstructionSet = SparcInstrInfo;
let AssemblyParsers = [SparcAsmParser];
let AssemblyWriters = [SparcAsmWriter];
+ let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZ.td b/llvm/lib/Target/SystemZ/SystemZ.td
index 06905fb..3800f7a 100644
--- a/llvm/lib/Target/SystemZ/SystemZ.td
+++ b/llvm/lib/Target/SystemZ/SystemZ.td
@@ -75,4 +75,5 @@
def SystemZ : Target {
let InstructionSet = SystemZInstrInfo;
let AssemblyParsers = [SystemZAsmParser];
+ let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 649851a..a701788 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1130,4 +1130,5 @@
let InstructionSet = X86InstrInfo;
let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
+ let AllowRegisterRenaming = 1;
}
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index 6a13367..9a72e71 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -1383,7 +1383,6 @@
// Change from the pseudo instruction to the concrete instruction.
MI.getOperand(0).setReg(getSTReg(Op1));
- MI.getOperand(0).setIsRenamable(false);
MI.RemoveOperand(1);
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
@@ -1411,7 +1410,6 @@
MI.RemoveOperand(0);
MI.RemoveOperand(1);
MI.getOperand(0).setReg(getSTReg(Op1));
- MI.getOperand(0).setIsRenamable(false);
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
// If we kill the second operand, make sure to pop it from the stack.
@@ -1628,7 +1626,6 @@
else
// Operand with a single register class constraint ("t" or "u").
Op.setReg(X86::ST0 + FPReg);
- Op.setIsRenamable(false);
}
// Simulate the inline asm popping its inputs and pushing its outputs.