Fix two typos I found in comments.
llvm-svn: 9806
diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
index 1a48d9c..84dc92e 100644
--- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
@@ -760,7 +760,7 @@
RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
#else
- // Default to using register g2 for holding large offsets
+ // Default to using register g4 for holding large offsets
OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
SparcIntRegClass::g4);
#endif
@@ -845,7 +845,7 @@
RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
#else
- // Default to using register g2 for holding large offsets
+ // Default to using register g4 for holding large offsets
OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
SparcIntRegClass::g4);
#endif
diff --git a/llvm/lib/Target/Sparc/SparcV9_Reg.td b/llvm/lib/Target/Sparc/SparcV9_Reg.td
index 40aaac4..6d5ad1d 100644
--- a/llvm/lib/Target/Sparc/SparcV9_Reg.td
+++ b/llvm/lib/Target/Sparc/SparcV9_Reg.td
@@ -32,7 +32,7 @@
// For fun, specify a register class.
//
-// FIXME: the register order should be defined in terms of the prefered
+// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,