Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
This commit might have caused regression on ppc64. Revert it to verify that.
llvm-svn: 320712
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 6be1373..f3017ac 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1053,10 +1053,7 @@
dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI);
);
- assert((BotRPTracker.getPos() == RegionEnd ||
- (RegionEnd->isDebugValue() &&
- BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&
- "Can't find the region bottom");
+ assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
// Cache the list of excess pressure sets in this region. This will also track
// the max pressure in the scheduled code for these sets.
@@ -1462,8 +1459,7 @@
RegOpers.detectDeadDefs(*MI, *LIS);
}
- if (BotRPTracker.getPos() != CurrentBottom)
- BotRPTracker.recedeSkipDebugValues();
+ BotRPTracker.recedeSkipDebugValues();
SmallVector<RegisterMaskPair, 8> LiveUses;
BotRPTracker.recede(RegOpers, &LiveUses);
assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");