[AArch, PowerPC] add more tests for legal rotate ops; NFC
llvm-svn: 337964
diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
index 41317ed..b238504 100644
--- a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
@@ -62,13 +62,23 @@
ret i32 %f
}
+define i64 @rotl_i64(i64 %x, i64 %z) {
+; CHECK-LABEL: rotl_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
+; CHECK-NEXT: rotld 3, 3, 4
+; CHECK-NEXT: blr
+ %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
+ ret i64 %f
+}
+
; Vector rotate.
define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
; CHECK-LABEL: rotl_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-NEXT: addi 3, 3, .LCPI4_0@toc@l
+; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha
+; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l
; CHECK-NEXT: lvx 4, 0, 3
; CHECK-NEXT: vsubuwm 4, 4, 3
; CHECK-NEXT: vslw 3, 2, 3
@@ -135,6 +145,17 @@
ret i16 %f
}
+define i32 @rotr_i32(i32 %x, i32 %z) {
+; CHECK-LABEL: rotr_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: subfic 4, 4, 32
+; CHECK-NEXT: clrlwi 4, 4, 27
+; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
+; CHECK-NEXT: blr
+ %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
+ ret i32 %f
+}
+
define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK-LABEL: rotr_i64:
; CHECK: # %bb.0:
@@ -151,8 +172,8 @@
define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
; CHECK-LABEL: rotr_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: addis 3, 2, .LCPI10_0@toc@ha
-; CHECK-NEXT: addi 3, 3, .LCPI10_0@toc@l
+; CHECK-NEXT: addis 3, 2, .LCPI12_0@toc@ha
+; CHECK-NEXT: addi 3, 3, .LCPI12_0@toc@l
; CHECK-NEXT: lvx 4, 0, 3
; CHECK-NEXT: vsubuwm 4, 4, 3
; CHECK-NEXT: vsrw 3, 2, 3