AMDGPU: Remove register operand from si_mask_branch
It isn't used for anything, and is also misleading since
it could be spilled at the end of the block, so it can't be relied
on. There ends up being a verifier error about using an undefined
register since the spill kills the register.
llvm-svn: 279899
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index c3db9d7..a435598 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -136,8 +136,7 @@
// be used later when inserting skips.
MachineInstr *NewBr =
BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
- .addOperand(MI.getOperand(2))
- .addReg(SaveExecReg, getKillRegState(SaveExec.isKill()));
+ .addOperand(MI.getOperand(2));
if (!LIS) {
MI.eraseFromParent();
@@ -196,8 +195,7 @@
// Insert a pseudo terminator to help keep the verifier happy.
MachineInstr *Branch =
BuildMI(MBB, Term, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
- .addMBB(DestBB)
- .addReg(DstReg);
+ .addMBB(DestBB);
if (!LIS) {
MI.eraseFromParent();