[SystemZ] Support conditional sibling calls via BRCL
This adds a conditional variant of CallJG instruction, CallBRCL.
It can be used for conditional sibling calls. Unfortunately, due
to IfCvt limitations, it only really works well for functions without
arguments.
Author: koriakin
Differential Revision: http://reviews.llvm.org/D18864
llvm-svn: 265814
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 80393a6..8bb548e 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -510,7 +510,8 @@
unsigned Opcode = MI.getOpcode();
if (STI.hasLoadStoreOnCond() && getConditionalMove(Opcode))
return true;
- if (Opcode == SystemZ::Return)
+ if (Opcode == SystemZ::Return ||
+ Opcode == SystemZ::CallJG)
return true;
return false;
}
@@ -571,6 +572,19 @@
.addReg(SystemZ::CC, RegState::Implicit);
return true;
}
+ if (Opcode == SystemZ::CallJG) {
+ const GlobalValue *Global = MI.getOperand(0).getGlobal();
+ const uint32_t *RegMask = MI.getOperand(1).getRegMask();
+ MI.RemoveOperand(1);
+ MI.RemoveOperand(0);
+ MI.setDesc(get(SystemZ::CallBRCL));
+ MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+ .addImm(CCValid).addImm(CCMask)
+ .addGlobalAddress(Global)
+ .addRegMask(RegMask)
+ .addReg(SystemZ::CC, RegState::Implicit);
+ return true;
+ }
return false;
}