[SystemZ] Add ALRK, AGLRK, SLRK and SGLRK
Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.
llvm-svn: 186689
diff --git a/llvm/test/CodeGen/SystemZ/int-add-08.ll b/llvm/test/CodeGen/SystemZ/int-add-08.ll
index d645137..bcef914 100644
--- a/llvm/test/CodeGen/SystemZ/int-add-08.ll
+++ b/llvm/test/CodeGen/SystemZ/int-add-08.ll
@@ -1,6 +1,7 @@
; Test 128-bit addition in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i128 *@foo()
diff --git a/llvm/test/CodeGen/SystemZ/int-add-09.ll b/llvm/test/CodeGen/SystemZ/int-add-09.ll
index 43136bd..717fed0 100644
--- a/llvm/test/CodeGen/SystemZ/int-add-09.ll
+++ b/llvm/test/CodeGen/SystemZ/int-add-09.ll
@@ -1,6 +1,6 @@
; Test 128-bit addition in which the second operand is constant.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check additions of 1. The XOR ensures that we don't instead load the
; constant into a register and use memory addition.
diff --git a/llvm/test/CodeGen/SystemZ/int-add-16.ll b/llvm/test/CodeGen/SystemZ/int-add-16.ll
new file mode 100644
index 0000000..409729f
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/int-add-16.ll
@@ -0,0 +1,22 @@
+; Test 128-bit addition when the distinct-operands facility is available.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Test the case where both operands are in registers.
+define i64 @f1(i64 %a, i64 %b, i64 %c, i64 %d, i64 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: algrk %r2, %r4, %r5
+; CHECK: alcgr
+; CHECK: br %r14
+ %x1 = insertelement <2 x i64> undef, i64 %b, i32 0
+ %x2 = insertelement <2 x i64> %x1, i64 %c, i32 1
+ %x = bitcast <2 x i64> %x2 to i128
+ %y2 = insertelement <2 x i64> %x1, i64 %d, i32 1
+ %y = bitcast <2 x i64> %y2 to i128
+ %add = add i128 %x, %y
+ %addv = bitcast i128 %add to <2 x i64>
+ %high = extractelement <2 x i64> %addv, i32 0
+ store i64 %high, i64 *%ptr
+ %low = extractelement <2 x i64> %addv, i32 1
+ ret i64 %low
+}
diff --git a/llvm/test/CodeGen/SystemZ/int-sub-05.ll b/llvm/test/CodeGen/SystemZ/int-sub-05.ll
index 9ec66d0..85ea14c 100644
--- a/llvm/test/CodeGen/SystemZ/int-sub-05.ll
+++ b/llvm/test/CodeGen/SystemZ/int-sub-05.ll
@@ -1,6 +1,7 @@
-; Test 128-bit addition in which the second operand is variable.
+; Test 128-bit subtraction in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i128 *@foo()
diff --git a/llvm/test/CodeGen/SystemZ/int-sub-09.ll b/llvm/test/CodeGen/SystemZ/int-sub-09.ll
new file mode 100644
index 0000000..00a60d3
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/int-sub-09.ll
@@ -0,0 +1,22 @@
+; Test 128-bit subtraction when the distinct-operands facility is available.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Test the case where both operands are in registers.
+define i64 @f1(i64 %a, i64 %b, i64 %c, i64 %d, i64 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: slgrk %r2, %r4, %r5
+; CHECK: slbgr
+; CHECK: br %r14
+ %x1 = insertelement <2 x i64> undef, i64 %b, i32 0
+ %x2 = insertelement <2 x i64> %x1, i64 %c, i32 1
+ %x = bitcast <2 x i64> %x2 to i128
+ %y2 = insertelement <2 x i64> %x1, i64 %d, i32 1
+ %y = bitcast <2 x i64> %y2 to i128
+ %sub = sub i128 %x, %y
+ %subv = bitcast i128 %sub to <2 x i64>
+ %high = extractelement <2 x i64> %subv, i32 0
+ store i64 %high, i64 *%ptr
+ %low = extractelement <2 x i64> %subv, i32 1
+ ret i64 %low
+}