commit faeaedf8e938696497021adcd5925e5741c72f62
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jun 24 16:16:12 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jun 24 16:16:12 2019 +0000
tree 66d3c65d42cfac2b080183c6c79562d0c205b23f
parent 906d494b6e7eb0d8bde19bec2de7d93a9516ebe3

GlobalISel: Remove unsigned variant of SrcOp

Force using Register.

One downside is the generated register enums require explicit
conversion.

llvm-svn: 364194

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index c996312..99143a4 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -195,7 +195,7 @@
   return true;
 }
 
-unsigned CallLowering::ValueHandler::extendRegister(unsigned ValReg,
+Register CallLowering::ValueHandler::extendRegister(Register ValReg,
                                                     CCValAssign &VA) {
   LLT LocTy{VA.getLocVT()};
   if (LocTy.getSizeInBits() == MRI.getType(ValReg).getSizeInBits())