commit faeaedf8e938696497021adcd5925e5741c72f62
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jun 24 16:16:12 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jun 24 16:16:12 2019 +0000
tree 66d3c65d42cfac2b080183c6c79562d0c205b23f
parent 906d494b6e7eb0d8bde19bec2de7d93a9516ebe3

GlobalISel: Remove unsigned variant of SrcOp

Force using Register.

One downside is the generated register enums require explicit
conversion.

llvm-svn: 364194

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index ca415833..81ead53 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -835,12 +835,12 @@
     auto SegmentNull = MIRBuilder.buildConstant(DstTy, NullVal);
     auto FlatNull = MIRBuilder.buildConstant(SrcTy, 0);
 
-    unsigned PtrLo32 = MRI.createGenericVirtualRegister(DstTy);
+    Register PtrLo32 = MRI.createGenericVirtualRegister(DstTy);
 
     // Extract low 32-bits of the pointer.
     MIRBuilder.buildExtract(PtrLo32, Src, 0);
 
-    unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
+    Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
     MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
     MIRBuilder.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
 
@@ -856,15 +856,15 @@
   auto FlatNull =
       MIRBuilder.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
 
-  unsigned ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder);
+  Register ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder);
 
-  unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
+  Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
   MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
 
-  unsigned BuildPtr = MRI.createGenericVirtualRegister(DstTy);
+  Register BuildPtr = MRI.createGenericVirtualRegister(DstTy);
 
   // Coerce the type of the low half of the result so we can use merge_values.
-  unsigned SrcAsInt = MRI.createGenericVirtualRegister(LLT::scalar(32));
+  Register SrcAsInt = MRI.createGenericVirtualRegister(LLT::scalar(32));
   MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT)
     .addDef(SrcAsInt)
     .addUse(Src);
@@ -883,7 +883,7 @@
   MachineIRBuilder &MIRBuilder) const {
   MIRBuilder.setInstr(MI);
 
-  unsigned Src = MI.getOperand(1).getReg();
+  Register Src = MI.getOperand(1).getReg();
   LLT Ty = MRI.getType(Src);
   assert(Ty.isScalar() && Ty.getSizeInBits() == 64);
 
@@ -913,7 +913,7 @@
   const LLT S1 = LLT::scalar(1);
   const LLT S64 = LLT::scalar(64);
 
-  unsigned Src = MI.getOperand(1).getReg();
+  Register Src = MI.getOperand(1).getReg();
   assert(MRI.getType(Src) == S64);
 
   // result = trunc(src)
@@ -959,12 +959,12 @@
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
 
-  unsigned Src = MI.getOperand(1).getReg();
+  Register Src = MI.getOperand(1).getReg();
   assert(MRI.getType(Src) == S64);
 
   // TODO: Should this use extract since the low half is unused?
   auto Unmerge = B.buildUnmerge({S32, S32}, Src);
-  unsigned Hi = Unmerge.getReg(1);
+  Register Hi = Unmerge.getReg(1);
 
   // Extract the upper half, since this is where we will find the sign and
   // exponent.
@@ -1001,8 +1001,8 @@
   MachineIRBuilder &B, bool Signed) const {
   B.setInstr(MI);
 
-  unsigned Dst = MI.getOperand(0).getReg();
-  unsigned Src = MI.getOperand(1).getReg();
+  Register Dst = MI.getOperand(0).getReg();
+  Register Src = MI.getOperand(1).getReg();
 
   const LLT S64 = LLT::scalar(64);
   const LLT S32 = LLT::scalar(32);