GlobalISel: Remove unsigned variant of SrcOp
Force using Register.
One downside is the generated register enums require explicit
conversion.
llvm-svn: 364194
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp
index 097ad0d..dc4eaf8 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -93,7 +93,7 @@
void assignValueToReg(Register ValVReg, const CCValAssign &VA,
const EVT &VT) override;
- unsigned getStackAddress(const CCValAssign &VA,
+ Register getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) override;
void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
@@ -134,7 +134,7 @@
const EVT &VT) {
const MipsSubtarget &STI =
static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
- unsigned PhysReg = VA.getLocReg();
+ Register PhysReg = VA.getLocReg();
if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
const MipsSubtarget &STI =
static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
@@ -173,7 +173,7 @@
}
}
-unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA,
+Register IncomingValueHandler::getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) {
MachineFunction &MF = MIRBuilder.getMF();
unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
@@ -188,7 +188,7 @@
unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Align);
- unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
+ Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
MIRBuilder.buildFrameIndex(AddrReg, FI);
return AddrReg;
@@ -228,7 +228,7 @@
void assignValueToReg(Register ValVReg, const CCValAssign &VA,
const EVT &VT) override;
- unsigned getStackAddress(const CCValAssign &VA,
+ Register getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) override;
void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
@@ -237,7 +237,7 @@
ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
Register ArgsReg, const EVT &VT) override;
- unsigned extendRegister(Register ValReg, const CCValAssign &VA);
+ Register extendRegister(Register ValReg, const CCValAssign &VA);
MachineInstrBuilder &MIB;
};
@@ -274,13 +274,13 @@
.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
*STI.getRegBankInfo());
} else {
- unsigned ExtReg = extendRegister(ValVReg, VA);
+ Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
MIB.addUse(PhysReg, RegState::Implicit);
}
}
-unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
+Register OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) {
MachineFunction &MF = MIRBuilder.getMF();
const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
@@ -288,7 +288,7 @@
LLT p0 = LLT::pointer(0, 32);
LLT s32 = LLT::scalar(32);
Register SPReg = MRI.createGenericVirtualRegister(p0);
- MIRBuilder.buildCopy(SPReg, Mips::SP);
+ MIRBuilder.buildCopy(SPReg, Register(Mips::SP));
Register OffsetReg = MRI.createGenericVirtualRegister(s32);
unsigned Offset = VA.getLocMemOffset();
@@ -310,11 +310,11 @@
const CCValAssign &VA) {
MachineMemOperand *MMO;
Register Addr = getStackAddress(VA, MMO);
- unsigned ExtReg = extendRegister(ValVReg, VA);
+ Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildStore(ExtReg, Addr, *MMO);
}
-unsigned OutgoingValueHandler::extendRegister(Register ValReg,
+Register OutgoingValueHandler::extendRegister(Register ValReg,
const CCValAssign &VA) {
LLT LocTy{VA.getLocVT()};
switch (VA.getLocInfo()) {
@@ -530,7 +530,7 @@
Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
MIB.addDef(Mips::SP, RegState::Implicit);
if (IsCalleeGlobalPIC) {
- unsigned CalleeReg =
+ Register CalleeReg =
MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32));
MachineInstr *CalleeGlobalValue =
MIRBuilder.buildGlobalValue(CalleeReg, Callee.getGlobal());
@@ -583,8 +583,8 @@
if (IsCalleeGlobalPIC) {
MIRBuilder.buildCopy(
- Mips::GP,
- MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel());
+ Register(Mips::GP),
+ MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel());
MIB.addDef(Mips::GP, RegState::Implicit);
}
MIRBuilder.insertInstr(MIB);
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.h b/llvm/lib/Target/Mips/MipsCallLowering.h
index 4eacb7c..4ed75a3 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.h
+++ b/llvm/lib/Target/Mips/MipsCallLowering.h
@@ -45,7 +45,7 @@
private:
bool assign(Register VReg, const CCValAssign &VA, const EVT &VT);
- virtual unsigned getStackAddress(const CCValAssign &VA,
+ virtual Register getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) = 0;
virtual void assignValueToReg(Register ValVReg, const CCValAssign &VA,
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index fe01b15..8e597dc 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -38,7 +38,7 @@
private:
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
- bool materialize32BitImm(unsigned DestReg, APInt Imm,
+ bool materialize32BitImm(Register DestReg, APInt Imm,
MachineIRBuilder &B) const;
bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
@@ -80,7 +80,7 @@
bool MipsInstructionSelector::selectCopy(MachineInstr &I,
MachineRegisterInfo &MRI) const {
- unsigned DstReg = I.getOperand(0).getReg();
+ Register DstReg = I.getOperand(0).getReg();
if (TargetRegisterInfo::isPhysicalRegister(DstReg))
return true;
@@ -104,12 +104,12 @@
return true;
}
-bool MipsInstructionSelector::materialize32BitImm(unsigned DestReg, APInt Imm,
+bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
MachineIRBuilder &B) const {
assert(Imm.getBitWidth() == 32 && "Unsupported immediate size.");
// Ori zero extends immediate. Used for values with zeros in high 16 bits.
if (Imm.getHiBits(16).isNullValue()) {
- MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Mips::ZERO})
+ MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
.addImm(Imm.getLoBits(16).getLimitedValue());
return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
}
@@ -121,12 +121,12 @@
}
// ADDiu sign extends immediate. Used for values with 1s in high 17 bits.
if (Imm.isSignedIntN(16)) {
- MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Mips::ZERO})
+ MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
.addImm(Imm.getLoBits(16).getLimitedValue());
return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
}
// Values that cannot be materialized with single immediate instruction.
- unsigned LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
+ Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {})
.addImm(Imm.getHiBits(16).getLimitedValue());
MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg})
@@ -201,7 +201,7 @@
switch (I.getOpcode()) {
case G_UMULH: {
- unsigned PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
+ Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
MachineInstr *PseudoMULTu, *PseudoMove;
PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
@@ -242,7 +242,7 @@
break;
}
case G_PHI: {
- const unsigned DestReg = I.getOperand(0).getReg();
+ const Register DestReg = I.getOperand(0).getReg();
const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
@@ -257,7 +257,7 @@
case G_LOAD:
case G_ZEXTLOAD:
case G_SEXTLOAD: {
- const unsigned DestReg = I.getOperand(0).getReg();
+ const Register DestReg = I.getOperand(0).getReg();
const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
const unsigned OpMemSizeInBytes = (*I.memoperands_begin())->getSize();
@@ -281,7 +281,7 @@
case G_UREM:
case G_SDIV:
case G_SREM: {
- unsigned HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
+ Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV;
bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV;
@@ -328,7 +328,7 @@
unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
if (Size == 32) {
- unsigned GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
MachineIRBuilder B(I);
if (!materialize32BitImm(GPRReg, APImm, B))
return false;
@@ -339,8 +339,8 @@
return false;
}
if (Size == 64) {
- unsigned GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass);
- unsigned GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass);
MachineIRBuilder B(I);
if (!materialize32BitImm(GPRRegHigh, APImm.getHiBits(32).trunc(32), B))
return false;
@@ -419,7 +419,7 @@
return false;
if (GVal->hasLocalLinkage()) {
- unsigned LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
LWGOT->getOperand(0).setReg(LWGOTDef);
MachineInstr *ADDiu =
@@ -432,7 +432,7 @@
return false;
}
} else {
- unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
.addDef(LUiReg)
@@ -455,8 +455,9 @@
}
case G_ICMP: {
struct Instr {
- unsigned Opcode, Def, LHS, RHS;
- Instr(unsigned Opcode, unsigned Def, unsigned LHS, unsigned RHS)
+ unsigned Opcode;
+ Register Def, LHS, RHS;
+ Instr(unsigned Opcode, Register Def, Register LHS, Register RHS)
: Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){};
bool hasImm() const {
@@ -467,10 +468,10 @@
};
SmallVector<struct Instr, 2> Instructions;
- unsigned ICMPReg = I.getOperand(0).getReg();
- unsigned Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
- unsigned LHS = I.getOperand(2).getReg();
- unsigned RHS = I.getOperand(3).getReg();
+ Register ICMPReg = I.getOperand(0).getReg();
+ Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ Register LHS = I.getOperand(2).getReg();
+ Register RHS = I.getOperand(3).getReg();
CmpInst::Predicate Cond =
static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp
index d489fac..85b20fc 100644
--- a/llvm/lib/Target/Mips/MipsMachineFunction.cpp
+++ b/llvm/lib/Target/Mips/MipsMachineFunction.cpp
@@ -44,14 +44,14 @@
return Mips::GPR32RegClass;
}
-unsigned MipsFunctionInfo::getGlobalBaseReg() {
+Register MipsFunctionInfo::getGlobalBaseReg() {
if (!GlobalBaseReg)
GlobalBaseReg =
MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF));
return GlobalBaseReg;
}
-unsigned MipsFunctionInfo::getGlobalBaseRegForGlobalISel() {
+Register MipsFunctionInfo::getGlobalBaseRegForGlobalISel() {
if (!GlobalBaseReg) {
getGlobalBaseReg();
initGlobalBaseReg();
diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.h b/llvm/lib/Target/Mips/MipsMachineFunction.h
index d9d53c8..aaa1e0e 100644
--- a/llvm/lib/Target/Mips/MipsMachineFunction.h
+++ b/llvm/lib/Target/Mips/MipsMachineFunction.h
@@ -32,8 +32,8 @@
void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
bool globalBaseRegSet() const;
- unsigned getGlobalBaseReg();
- unsigned getGlobalBaseRegForGlobalISel();
+ Register getGlobalBaseReg();
+ Register getGlobalBaseRegForGlobalISel();
// Insert instructions to initialize the global base register in the
// first MBB of the function.