Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
llvm-svn: 148337
diff --git a/llvm/test/CodeGen/CellSPU/rotate_ops.ll b/llvm/test/CodeGen/CellSPU/rotate_ops.ll
index b1219e6..8b7af20 100644
--- a/llvm/test/CodeGen/CellSPU/rotate_ops.ll
+++ b/llvm/test/CodeGen/CellSPU/rotate_ops.ll
@@ -1,5 +1,5 @@
; RUN: llc < %s -march=cellspu -o %t1.s
-; RUN: grep rot %t1.s | count 86
+; RUN: grep rot %t1.s | count 85
; RUN: grep roth %t1.s | count 8
; RUN: grep roti.*5 %t1.s | count 1
; RUN: grep roti.*27 %t1.s | count 1
@@ -163,7 +163,7 @@
define <2 x float> @test1(<4 x float> %param )
{
; CHECK: test1
-; CHECK: rotqbyi
+; CHECK: shufb
%el = extractelement <4 x float> %param, i32 1
%vec1 = insertelement <1 x float> undef, float %el, i32 0
%rv = shufflevector <1 x float> %vec1, <1 x float> undef, <2 x i32><i32 0,i32 0>
diff --git a/llvm/test/CodeGen/X86/avx-shuffle.ll b/llvm/test/CodeGen/X86/avx-shuffle.ll
index 232fc78..ee038ce 100644
--- a/llvm/test/CodeGen/X86/avx-shuffle.ll
+++ b/llvm/test/CodeGen/X86/avx-shuffle.ll
@@ -12,11 +12,11 @@
; rdar://10538417
define <3 x i64> @test2(<2 x i64> %v) nounwind readnone {
; CHECK: test2:
-; CHECK: vxorpd
-; CHECK: vperm2f128
+; CHECK: vinsertf128
%1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef>
%2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2>
ret <3 x i64> %2
+; CHECK: ret
}
define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
@@ -24,6 +24,7 @@
ret <4 x i64> %c
; CHECK: test3:
; CHECK: vperm2f128
+; CHECK: ret
}
define <8 x float> @test4(float %a) nounwind {
@@ -75,3 +76,23 @@
; CHECK: ret
ret void
}
+
+; Extract a value from a shufflevector..
+define i32 @test9(<4 x i32> %a) nounwind {
+; CHECK: test9
+; CHECK: vpextrd
+ %b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 undef, i32 4>
+ %r = extractelement <8 x i32> %b, i32 2
+; CHECK: ret
+ ret i32 %r
+}
+
+; Extract a value which is the result of an undef mask.
+define i32 @test10(<4 x i32> %a) nounwind {
+; CHECK: @test10
+; CHECK-NEXT: #
+; CHECK-NEXT: ret
+ %b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %r = extractelement <8 x i32> %b, i32 2
+ ret i32 %r
+}
diff --git a/llvm/test/CodeGen/X86/widen_shuffle-1.ll b/llvm/test/CodeGen/X86/widen_shuffle-1.ll
index 24608d0..7bebb27 100644
--- a/llvm/test/CodeGen/X86/widen_shuffle-1.ll
+++ b/llvm/test/CodeGen/X86/widen_shuffle-1.ll
@@ -10,6 +10,7 @@
%val = fadd <3 x float> %x, %src2
store <3 x float> %val, <3 x float>* %dst.addr
ret void
+; CHECK: ret
}
@@ -23,6 +24,7 @@
%val = fadd <3 x float> %x, %src2
store <3 x float> %val, <3 x float>* %dst.addr
ret void
+; CHECK: ret
}
; Example of when widening a v3float operation causes the DAG to replace a node
@@ -31,7 +33,7 @@
define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind {
entry:
; CHECK: shuf3:
-; CHECK: pshufd
+; CHECK: shufps
%shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
%tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
%tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -45,6 +47,7 @@
%shuffle.i.i.i21 = shufflevector <4 x float> %tmp2.i18, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
store <4 x float> %shuffle.i.i.i21, <4 x float>* %dst
ret void
+; CHECK: ret
}
; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
@@ -53,6 +56,7 @@
; CHECK-NOT: punpckldq
%vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i8> %vshuf
+; CHECK: ret
}
; PR11389: another CONCAT_VECTORS case
@@ -61,4 +65,5 @@
%v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
store <8 x i8> %v, <8 x i8>* %p, align 8
ret void
+; CHECK: ret
}