[llvm-exegesis] Provide a way to handle memory instructions.
Summary:
And implement memory instructions on X86.
This fixes PR36906.
Reviewers: gchatelet
Reviewed By: gchatelet
Subscribers: lebedev.ri, filcab, mgorny, tschuett, RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D48935
llvm-svn: 338567
diff --git a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
index 5c417e3..bdfa5a7 100644
--- a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -109,6 +109,48 @@
PM.add(llvm::createX86FloatingPointStackifierPass());
}
+ unsigned getScratchMemoryRegister(const llvm::Triple &TT) const override {
+ if (!TT.isArch64Bit()) {
+ // FIXME: This would require popping from the stack, so we would have to
+ // add some additional setup code.
+ return 0;
+ }
+ return TT.isOSWindows() ? llvm::X86::RCX : llvm::X86::RDI;
+ }
+
+ unsigned getMaxMemoryAccessSize() const override { return 64; }
+
+ void fillMemoryOperands(InstructionInstance &II, unsigned Reg,
+ unsigned Offset) const override {
+ // FIXME: For instructions that read AND write to memory, we use the same
+ // value for input and output.
+ for (size_t I = 0, E = II.Instr.Operands.size(); I < E; ++I) {
+ const Operand *Op = &II.Instr.Operands[I];
+ if (Op->IsExplicit && Op->IsMem) {
+ // Case 1: 5-op memory.
+ assert((I + 5 <= E) && "x86 memory references are always 5 ops");
+ II.getValueFor(*Op) = llvm::MCOperand::createReg(Reg); // BaseReg
+ Op = &II.Instr.Operands[++I];
+ assert(Op->IsMem);
+ assert(Op->IsExplicit);
+ II.getValueFor(*Op) = llvm::MCOperand::createImm(1); // ScaleAmt
+ Op = &II.Instr.Operands[++I];
+ assert(Op->IsMem);
+ assert(Op->IsExplicit);
+ II.getValueFor(*Op) = llvm::MCOperand::createReg(0); // IndexReg
+ Op = &II.Instr.Operands[++I];
+ assert(Op->IsMem);
+ assert(Op->IsExplicit);
+ II.getValueFor(*Op) = llvm::MCOperand::createImm(Offset); // Disp
+ Op = &II.Instr.Operands[++I];
+ assert(Op->IsMem);
+ assert(Op->IsExplicit);
+ II.getValueFor(*Op) = llvm::MCOperand::createReg(0); // Segment
+ // Case2: segment:index addressing. We assume that ES is 0.
+ }
+ }
+ }
+
std::vector<llvm::MCInst> setRegToConstant(const llvm::MCSubtargetInfo &STI,
unsigned Reg) const override {
// GPR.