[Hexagon] Start using regmasks on calls
All the cool targets are doing it...
llvm-svn: 295371
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 3608099..5f375f8 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -440,17 +440,21 @@
// Put instructions that last defined integer or double registers into the
// map.
- for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
- MachineOperand &Op = MI.getOperand(I);
- if (!Op.isReg() || !Op.isDef() || !Op.getReg())
- continue;
- unsigned Reg = Op.getReg();
- if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- LastDef[*SubRegs] = &MI;
- }
- } else if (Hexagon::IntRegsRegClass.contains(Reg))
- LastDef[Reg] = &MI;
+ for (MachineOperand &Op : MI.operands()) {
+ if (Op.isReg()) {
+ if (!Op.isDef() || !Op.getReg())
+ continue;
+ unsigned Reg = Op.getReg();
+ if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
+ for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
+ LastDef[*SubRegs] = &MI;
+ } else if (Hexagon::IntRegsRegClass.contains(Reg))
+ LastDef[Reg] = &MI;
+ } else if (Op.isRegMask()) {
+ for (unsigned Reg : Hexagon::IntRegsRegClass)
+ if (Op.clobbersPhysReg(Reg))
+ LastDef[Reg] = &MI;
+ }
}
}
}