Do really not unroll the vector loop in combination with register tiling
The previous commit lacked a test case for register tiling + pre-vectorization
and we obviously got it immediately wrong.
llvm-svn: 245599
diff --git a/polly/lib/Transform/ScheduleOptimizer.cpp b/polly/lib/Transform/ScheduleOptimizer.cpp
index 4fcc4e4..1061447 100644
--- a/polly/lib/Transform/ScheduleOptimizer.cpp
+++ b/polly/lib/Transform/ScheduleOptimizer.cpp
@@ -306,12 +306,11 @@
isl_multi_val_set_val(Sizes, 0, isl_val_int_from_si(Ctx, VectorWidth));
Node = isl_schedule_node_band_tile(Node, Sizes);
Node = isl_schedule_node_child(Node, 0);
- Node = isl_schedule_node_band_sink(Node);
-
// Make sure the "trivially vectorizable loop" is not unrolled. Otherwise,
// we will have troubles to match it in the backend.
Node = isl_schedule_node_band_set_ast_build_options(
- Node, isl_union_set_read_from_str(Ctx, "{unroll[x]: 1 = 0}"));
+ Node, isl_union_set_read_from_str(Ctx, "{ unroll[x]: 1 = 0 }"));
+ Node = isl_schedule_node_band_sink(Node);
Node = isl_schedule_node_child(Node, 0);
return Node;
}