Fix MergeConsecutiveStore for non-byte-sized memory accesses.
The bug showed up as a compile-time assertion failure:
Assertion `NumBits >= MIN_INT_BITS && "bitwidth too small"' failed
when building msan tests on x86-64.
Prior to r236850, this bug was masked due to a bogus alignment check,
which also accidentally rejected non-byte-sized accesses. Afterwards,
an invalid ElementSizeBytes == 0 got further into the function, and
triggered the assertion failure.
It would probably be a good idea to allow it to handle merging stores
of unusual widths as well, but for now, to un-break it, I'm just
making the minimal fix.
Differential Revision: http://reviews.llvm.org/D9626
llvm-svn: 236927
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index bd61f0c..3728168 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10673,6 +10673,10 @@
bool NoVectors = DAG.getMachineFunction().getFunction()->hasFnAttribute(
Attribute::NoImplicitFloat);
+ // This function cannot currently deal with non-byte-sized memory sizes.
+ if (ElementSizeBytes * 8 != MemVT.getSizeInBits())
+ return false;
+
// Don't merge vectors into wider inputs.
if (MemVT.isVector() || !MemVT.isSimple())
return false;
diff --git a/llvm/test/CodeGen/X86/merge-consecutive-stores-i1.ll b/llvm/test/CodeGen/X86/merge-consecutive-stores-i1.ll
new file mode 100644
index 0000000..a7f5c21
--- /dev/null
+++ b/llvm/test/CodeGen/X86/merge-consecutive-stores-i1.ll
@@ -0,0 +1,15 @@
+; RUN: llc -march=x86-64 < %s
+
+; Ensure that MergeConsecutiveStores doesn't crash when dealing with
+; i1 operands.
+
+%struct.X = type { i1, i1 }
+
+@b = common global %struct.X zeroinitializer, align 4
+
+define void @foo() {
+entry:
+ store i1 0, i1* getelementptr inbounds (%struct.X, %struct.X* @b, i64 0, i32 0), align 4
+ store i1 0, i1* getelementptr inbounds (%struct.X, %struct.X* @b, i64 0, i32 1), align 1
+ ret void
+}