commit fdea5e02ce598be1cdda0259381039e8b5d6cba5
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Oct 01 02:23:20 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Oct 01 02:23:20 2019 +0000
tree 72813d8d277f088768ddff527a0cbc2c78748d10
parent b169ee2eca0e8349678feaa2686f55c30bf1d836

AMDGPU/GlobalISel: Select s1 src G_SITOFP/G_UITOFP

llvm-svn: 373298

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index e289e8e..10420d6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -417,9 +417,9 @@
                {S32, S8}, {S128, S32}, {S128, S64}, {S32, LLT::scalar(24)}})
     .scalarize(0);
 
-  // TODO: Legal for s1->s64, requires split for VALU.
+  // TODO: Split s1->s64 during regbankselect for VALU.
   getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
-    .legalFor({{S32, S32}, {S64, S32}, {S16, S32}, {S32, S1}, {S16, S1}})
+    .legalFor({{S32, S32}, {S64, S32}, {S16, S32}, {S32, S1}, {S16, S1}, {S64, S1}})
     .lowerFor({{S32, S64}})
     .customFor({{S64, S64}})
     .scalarize(0);