commit ff62819e2fdd0d3c1e11c981edfaaab33ce12d7b
author Rafael Espindola <rafael.espindola@gmail.com> Thu Oct 19 12:45:04 2006 +0000
committer Rafael Espindola <rafael.espindola@gmail.com> Thu Oct 19 12:45:04 2006 +0000
tree e995baf68a163db355715da6ebb1b8f82c7eb590
parent 3c563c5072607d5b09fe2456bc8c94bf07c88b1a

implement extloadi8 and extloadi16

llvm-svn: 31047

llvm/lib/Target/ARM/ARMInstrInfo.td

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 349c358..c16e3e8 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -160,6 +160,10 @@
                        "ldrb $dst, [$addr]",
                        [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
 
+def LDRB2   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+                       "ldrb $dst, [$addr]",
+                       [(set IntRegs:$dst, (extloadi8 IntRegs:$addr))]>;
+
 def LDRSB   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
                        "ldrsb $dst, [$addr]",
                        [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
@@ -168,6 +172,10 @@
                        "ldrh $dst, [$addr]",
                        [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
 
+def LDRH2   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+                       "ldrh $dst, [$addr]",
+                       [(set IntRegs:$dst, (extloadi16 IntRegs:$addr))]>;
+
 def LDRSH   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
                        "ldrsh $dst, [$addr]",
                        [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;