[SystemZ] Model access registers as LLVM registers
Add the 16 access registers as LLVM registers. This allows removing
a lot of special cases in the assembler and disassembler where we
were handling access registers; this can all just use the generic
register code now.
Also add a bunch of instructions to operate on access registers,
for assembler/disassembler use only. No change in code generation
intended.
llvm-svn: 286283
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index 3caff53..3f373de 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -43,7 +43,8 @@
FP128Reg,
VR32Reg,
VR64Reg,
- VR128Reg
+ VR128Reg,
+ AR32Reg,
};
enum MemoryKind {
@@ -61,7 +62,6 @@
KindInvalid,
KindToken,
KindReg,
- KindAccessReg,
KindImm,
KindImmTLS,
KindMem
@@ -116,7 +116,6 @@
union {
TokenOp Token;
RegOp Reg;
- unsigned AccessReg;
const MCExpr *Imm;
ImmTLSOp ImmTLS;
MemOp Mem;
@@ -155,12 +154,6 @@
return Op;
}
static std::unique_ptr<SystemZOperand>
- createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
- auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc);
- Op->AccessReg = Num;
- return Op;
- }
- static std::unique_ptr<SystemZOperand>
createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
Op->Imm = Expr;
@@ -212,12 +205,6 @@
return Reg.Num;
}
- // Access register operands. Access registers aren't exposed to LLVM
- // as registers.
- bool isAccessReg() const {
- return Kind == KindAccessReg;
- }
-
// Immediate operands.
bool isImm() const override {
return Kind == KindImm;
@@ -270,11 +257,6 @@
assert(N == 1 && "Invalid number of operands");
Inst.addOperand(MCOperand::createReg(getReg()));
}
- void addAccessRegOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands");
- assert(Kind == KindAccessReg && "Invalid operand type");
- Inst.addOperand(MCOperand::createImm(AccessReg));
- }
void addImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands");
addExpr(Inst, getImm());
@@ -337,6 +319,7 @@
bool isVR64() const { return isReg(VR64Reg); }
bool isVF128() const { return false; }
bool isVR128() const { return isReg(VR128Reg); }
+ bool isAR32() const { return isReg(AR32Reg); }
bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
@@ -372,7 +355,7 @@
RegGR,
RegFP,
RegV,
- RegAccess
+ RegAR
};
struct Register {
RegisterGroup Group;
@@ -477,6 +460,9 @@
OperandMatchResultTy parseVR128(OperandVector &Operands) {
return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
}
+ OperandMatchResultTy parseAR32(OperandVector &Operands) {
+ return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
+ }
OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
return parseAnyRegister(Operands);
}
@@ -498,7 +484,6 @@
OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
}
- OperandMatchResultTy parseAccessReg(OperandVector &Operands);
OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
}
@@ -631,7 +616,7 @@
else if (Prefix == 'v' && Reg.Num < 32)
Reg.Group = RegV;
else if (Prefix == 'a' && Reg.Num < 16)
- Reg.Group = RegAccess;
+ Reg.Group = RegAR;
else
return Error(Reg.StartLoc, "invalid register");
@@ -721,6 +706,10 @@
Kind = VR128Reg;
RegNo = SystemZMC::VR128Regs[Reg.Num];
}
+ else if (Reg.Group == RegAR) {
+ Kind = AR32Reg;
+ RegNo = SystemZMC::AR32Regs[Reg.Num];
+ }
else {
return MatchOperand_ParseFail;
}
@@ -1034,9 +1023,8 @@
RegNo = SystemZMC::FP64Regs[Reg.Num];
else if (Reg.Group == RegV)
RegNo = SystemZMC::VR128Regs[Reg.Num];
- else
- // FIXME: Access registers aren't modelled as LLVM registers yet.
- return Error(Reg.StartLoc, "invalid operand for instruction");
+ else if (Reg.Group == RegAR)
+ RegNo = SystemZMC::AR32Regs[Reg.Num];
StartLoc = Reg.StartLoc;
EndLoc = Reg.EndLoc;
return false;
@@ -1184,21 +1172,6 @@
}
OperandMatchResultTy
-SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
- if (Parser.getTok().isNot(AsmToken::Percent))
- return MatchOperand_NoMatch;
-
- Register Reg;
- if (parseRegister(Reg, RegAccess, nullptr))
- return MatchOperand_ParseFail;
-
- Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
- Reg.StartLoc,
- Reg.EndLoc));
- return MatchOperand_Success;
-}
-
-OperandMatchResultTy
SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
int64_t MaxVal, bool AllowTLS) {
MCContext &Ctx = getContext();