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gerrit-public.fairphone.software / toolchain / llvm-project / 00a4aaceccdf0d686423d6b5ea09b6c172979d7a / . / llvm / test / CodeGen / Mips / inlineasm-operand-code.ll
blob: d4481b1300c825c59b5d649e1651b32f4aeb72e7 [file] [log] [blame]
Eric Christophered51b9e2012-05-10 21:48:22 +0000[diff] [blame]1; Positive test for inline register constraints
2;
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]3; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=CHECK_LITTLE_32 %s
4; RUN: llc -march=mips < %s | FileCheck -check-prefix=CHECK_BIG_32 %s
Eric Christophered51b9e2012-05-10 21:48:22 +0000[diff] [blame]5
Jack Carterb2af5122012-07-05 23:58:21 +0000[diff] [blame]6%union.u_tag = type { i64 }
7%struct.anon = type { i32, i32 }
8@uval = common global %union.u_tag zeroinitializer, align 8
Eric Christophered51b9e2012-05-10 21:48:22 +0000[diff] [blame]9
10; X with -3
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]11define i32 @constraint_X() nounwind {
12entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]13;CHECK_LITTLE_32-LABEL: constraint_X:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]14;CHECK_LITTLE_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]15;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]16;CHECK_LITTLE_32: #NO_APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]17 tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ;
Eric Christophered51b9e2012-05-10 21:48:22 +0000[diff] [blame]18 ret i32 0
19}
Jack Carterb2af5122012-07-05 23:58:21 +0000[diff] [blame]20
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]21; x with -3
22define i32 @constraint_x() nounwind {
23entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]24;CHECK_LITTLE_32-LABEL: constraint_x:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]25;CHECK_LITTLE_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]26;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]27;CHECK_LITTLE_32: #NO_APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]28 tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ;
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]29 ret i32 0
30}
31
32; d with -3
33define i32 @constraint_d() nounwind {
34entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]35;CHECK_LITTLE_32-LABEL: constraint_d:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]36;CHECK_LITTLE_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]37;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]38;CHECK_LITTLE_32: #NO_APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]39 tail call i32 asm sideeffect "addiu $0, $1, ${2:d}", "=r,r,I"(i32 7, i32 -3) ;
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]40 ret i32 0
41}
42
43; m with -3
44define i32 @constraint_m() nounwind {
45entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]46;CHECK_LITTLE_32-LABEL: constraint_m:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]47;CHECK_LITTLE_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]48;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, -4
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]49;CHECK_LITTLE_32: #NO_APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]50 tail call i32 asm sideeffect "addiu $0, $1, ${2:m}", "=r,r,I"(i32 7, i32 -3) ;
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]51 ret i32 0
52}
53
54; z with -3
55define i32 @constraint_z() nounwind {
56entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]57;CHECK_LITTLE_32-LABEL: constraint_z:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]58;CHECK_LITTLE_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]59;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]60;CHECK_LITTLE_32: #NO_APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]61 tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ;
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]62
63; z with 0
64;CHECK_LITTLE_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]65;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]66;CHECK_LITTLE_32: #NO_APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]67 tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
Toma Tabacu27cab752014-11-06 14:25:42 +0000[diff] [blame]68
69; z with non-zero and the "r"(register) and "J"(integer zero) constraints
70;CHECK_LITTLE_32: #APP
71;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
72;CHECK_LITTLE_32: #NO_APP
73 call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
74
75; z with zero and the "r"(register) and "J"(integer zero) constraints
76;CHECK_LITTLE_32: #APP
77;CHECK_LITTLE_32: mtc0 $0, ${{[0-9]+}}
78;CHECK_LITTLE_32: #NO_APP
79 call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
80
81; z with non-zero and just the "r"(register) constraint
82;CHECK_LITTLE_32: #APP
83;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
84;CHECK_LITTLE_32: #NO_APP
85 call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
86
87; z with zero and just the "r"(register) constraint
88; FIXME: Check for $0, instead of other registers.
89; We should be using $0 directly in this case, not real registers.
90; When the materialization of 0 gets fixed, this test will fail.
91;CHECK_LITTLE_32: #APP
92;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
93;CHECK_LITTLE_32: #NO_APP
94 call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]95 ret i32 0
96}
97
98; a long long in 32 bit mode (use to assert)
99define i32 @constraint_longlong() nounwind {
100entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]101;CHECK_LITTLE_32-LABEL: constraint_longlong:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]102;CHECK_LITTLE_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]103;CHECK_LITTLE_32: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]104;CHECK_LITTLE_32: #NO_APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]105 tail call i64 asm sideeffect "addiu $0, $1, $2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]106 ret i32 0
107}
108
109; D, in little endian the source reg will be 4 bytes into the long long
110define i32 @constraint_D() nounwind {
111entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]112;CHECK_LITTLE_32-LABEL: constraint_D:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]113;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
114;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
115;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
116;CHECK_LITTLE_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]117;CHECK_LITTLE_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]118;CHECK_LITTLE_32: #NO_APP
119
120; D, in big endian the source reg will also be 4 bytes into the long long
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]121;CHECK_BIG_32-LABEL: constraint_D:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]122;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
123;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
124;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
125;CHECK_BIG_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]126;CHECK_BIG_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]127;CHECK_BIG_32: #NO_APP
David Blaikief72d05b2015-03-13 18:20:45 +0000[diff] [blame]128 %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]129 %trunc1 = trunc i64 %bosco to i32
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]130 tail call i32 asm sideeffect "or $0, ${1:D}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]131 ret i32 0
132}
133
134; L, in little endian the source reg will be 0 bytes into the long long
135define i32 @constraint_L() nounwind {
136entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]137;CHECK_LITTLE_32-LABEL: constraint_L:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]138;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
139;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
140;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
141;CHECK_LITTLE_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]142;CHECK_LITTLE_32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]143;CHECK_LITTLE_32: #NO_APP
144; L, in big endian the source reg will be 4 bytes into the long long
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]145;CHECK_BIG_32-LABEL: constraint_L:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]146;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
147;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
148;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
149;CHECK_BIG_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]150;CHECK_BIG_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]151;CHECK_BIG_32: #NO_APP
David Blaikief72d05b2015-03-13 18:20:45 +0000[diff] [blame]152 %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]153 %trunc1 = trunc i64 %bosco to i32
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]154 tail call i32 asm sideeffect "or $0, ${1:L}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]155 ret i32 0
156}
157
158; M, in little endian the source reg will be 4 bytes into the long long
159define i32 @constraint_M() nounwind {
160entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]161;CHECK_LITTLE_32-LABEL: constraint_M:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]162;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
163;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
164;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
165;CHECK_LITTLE_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]166;CHECK_LITTLE_32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]167;CHECK_LITTLE_32: #NO_APP
168; M, in big endian the source reg will be 0 bytes into the long long
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]169;CHECK_BIG_32-LABEL: constraint_M:
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]170;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
171;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
172;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
173;CHECK_BIG_32: #APP
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]174;CHECK_BIG_32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]175;CHECK_BIG_32: #NO_APP
David Blaikief72d05b2015-03-13 18:20:45 +0000[diff] [blame]176 %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]177 %trunc1 = trunc i64 %bosco to i32
Daniel Sanders00a4aac2015-11-16 14:14:59 +0000[diff] [blame^]178 tail call i32 asm sideeffect "or $0, ${1:M}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
Jack Cartera62ba822012-07-18 06:41:36 +0000[diff] [blame]179 ret i32 0
180}