NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 1 | //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 10 | #define DEBUG_TYPE "hexagon-disassembler" |
| 11 | |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 12 | #include "Hexagon.h" |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 13 | #include "MCTargetDesc/HexagonBaseInfo.h" |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 14 | #include "MCTargetDesc/HexagonMCChecker.h" |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 15 | #include "MCTargetDesc/HexagonMCTargetDesc.h" |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 16 | #include "MCTargetDesc/HexagonMCInstrInfo.h" |
| 17 | #include "MCTargetDesc/HexagonInstPrinter.h" |
| 18 | #include "llvm/ADT/StringExtras.h" |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 19 | #include "llvm/MC/MCDisassembler.h" |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 20 | #include "llvm/MC/MCContext.h" |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 21 | #include "llvm/MC/MCExpr.h" |
| 22 | #include "llvm/MC/MCFixedLenDisassembler.h" |
| 23 | #include "llvm/MC/MCInst.h" |
| 24 | #include "llvm/MC/MCInstrDesc.h" |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 25 | #include "llvm/MC/MCInstrInfo.h" |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 26 | #include "llvm/MC/MCSubtargetInfo.h" |
| 27 | #include "llvm/Support/Debug.h" |
| 28 | #include "llvm/Support/ErrorHandling.h" |
| 29 | #include "llvm/Support/LEB128.h" |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 30 | #include "llvm/Support/MemoryObject.h" |
Chandler Carruth | d990388 | 2015-01-14 11:23:27 +0000 | [diff] [blame] | 31 | #include "llvm/Support/raw_ostream.h" |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 32 | #include "llvm/Support/TargetRegistry.h" |
Chandler Carruth | d990388 | 2015-01-14 11:23:27 +0000 | [diff] [blame] | 33 | #include <vector> |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 34 | |
| 35 | using namespace llvm; |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 36 | using namespace Hexagon; |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 37 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 38 | typedef MCDisassembler::DecodeStatus DecodeStatus; |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 39 | |
| 40 | namespace { |
| 41 | /// \brief Hexagon disassembler for all Hexagon platforms. |
| 42 | class HexagonDisassembler : public MCDisassembler { |
| 43 | public: |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 44 | std::unique_ptr<MCInstrInfo const> const MCII; |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 45 | std::unique_ptr<MCInst *> CurrentBundle; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 46 | HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, |
| 47 | MCInstrInfo const *MCII) |
| 48 | : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 49 | |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 50 | DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, |
| 51 | ArrayRef<uint8_t> Bytes, uint64_t Address, |
| 52 | raw_ostream &VStream, raw_ostream &CStream, |
| 53 | bool &Complete) const; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 54 | DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, |
Rafael Espindola | 7fc5b87 | 2014-11-12 02:04:27 +0000 | [diff] [blame] | 55 | ArrayRef<uint8_t> Bytes, uint64_t Address, |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 56 | raw_ostream &VStream, |
| 57 | raw_ostream &CStream) const override; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 58 | |
| 59 | void adjustExtendedInstructions(MCInst &MCI, MCInst const &MCB) const; |
| 60 | void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 61 | }; |
Alexander Kornienko | f00654e | 2015-06-23 09:49:53 +0000 | [diff] [blame] | 62 | } |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 63 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 64 | // Forward declare these because the auto-generated code will reference them. |
| 65 | // Definitions are further down. |
| 66 | |
| 67 | static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 68 | uint64_t Address, |
| 69 | const void *Decoder); |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 70 | static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, |
| 71 | uint64_t Address, |
| 72 | const void *Decoder); |
| 73 | static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 74 | uint64_t Address, |
| 75 | const void *Decoder); |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 76 | static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 77 | uint64_t Address, |
| 78 | const void *Decoder); |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 79 | static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 80 | uint64_t Address, |
| 81 | const void *Decoder); |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 82 | static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 83 | uint64_t Address, |
| 84 | const void *Decoder); |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 85 | static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 86 | uint64_t Address, |
| 87 | const void *Decoder); |
Colin LeMahieu | f3db884 | 2014-12-19 19:06:32 +0000 | [diff] [blame] | 88 | static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 89 | uint64_t Address, |
| 90 | const void *Decoder); |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 91 | static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 92 | uint64_t Address, |
| 93 | const void *Decoder); |
Colin LeMahieu | 404d5b2 | 2015-02-10 16:59:36 +0000 | [diff] [blame] | 94 | static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 95 | uint64_t Address, |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 96 | const void *Decoder); |
| 97 | |
| 98 | static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn); |
| 99 | static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, |
| 100 | void const *Decoder); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 101 | |
| 102 | static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, |
| 103 | raw_ostream &os); |
Colin LeMahieu | f3db884 | 2014-12-19 19:06:32 +0000 | [diff] [blame] | 104 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 105 | static unsigned getRegFromSubinstEncoding(unsigned encoded_reg); |
| 106 | |
| 107 | static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, |
| 108 | uint64_t Address, const void *Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 109 | static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 110 | const void *Decoder); |
| 111 | static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 112 | const void *Decoder); |
| 113 | static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 114 | const void *Decoder); |
| 115 | static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 116 | const void *Decoder); |
| 117 | static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 118 | const void *Decoder); |
| 119 | static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 120 | const void *Decoder); |
| 121 | static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 122 | const void *Decoder); |
| 123 | static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 124 | const void *Decoder); |
| 125 | static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 126 | const void *Decoder); |
| 127 | static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 128 | const void *Decoder); |
| 129 | static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 130 | const void *Decoder); |
| 131 | static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 132 | const void *Decoder); |
| 133 | static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 134 | const void *Decoder); |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 135 | static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 136 | const void *Decoder); |
| 137 | static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 138 | const void *Decoder); |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 139 | static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 140 | const void *Decoder); |
Colin LeMahieu | efa74e0 | 2014-11-18 20:28:11 +0000 | [diff] [blame] | 141 | |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 142 | #include "HexagonGenDisassemblerTables.inc" |
| 143 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 144 | static MCDisassembler *createHexagonDisassembler(const Target &T, |
| 145 | const MCSubtargetInfo &STI, |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 146 | MCContext &Ctx) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 147 | return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | extern "C" void LLVMInitializeHexagonDisassembler() { |
| 151 | TargetRegistry::RegisterMCDisassembler(TheHexagonTarget, |
| 152 | createHexagonDisassembler); |
| 153 | } |
| 154 | |
| 155 | DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, |
Rafael Espindola | 7fc5b87 | 2014-11-12 02:04:27 +0000 | [diff] [blame] | 156 | ArrayRef<uint8_t> Bytes, |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 157 | uint64_t Address, |
| 158 | raw_ostream &os, |
| 159 | raw_ostream &cs) const { |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 160 | DecodeStatus Result = DecodeStatus::Success; |
| 161 | bool Complete = false; |
| 162 | Size = 0; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 163 | |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 164 | *CurrentBundle = &MI; |
Colin LeMahieu | f0af6e5 | 2015-11-13 17:42:46 +0000 | [diff] [blame] | 165 | MI = HexagonMCInstrInfo::createBundle(); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 166 | while (Result == Success && Complete == false) { |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 167 | if (Bytes.size() < HEXAGON_INSTR_SIZE) |
| 168 | return MCDisassembler::Fail; |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 169 | MCInst *Inst = new (getContext()) MCInst; |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 170 | Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); |
| 171 | MI.addOperand(MCOperand::createInst(Inst)); |
| 172 | Size += HEXAGON_INSTR_SIZE; |
| 173 | Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); |
| 174 | } |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 175 | if(Result == MCDisassembler::Fail) |
| 176 | return Result; |
| 177 | HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo()); |
| 178 | if(!Checker.check()) |
| 179 | return MCDisassembler::Fail; |
| 180 | return MCDisassembler::Success; |
| 181 | } |
| 182 | |
| 183 | namespace { |
| 184 | HexagonDisassembler const &disassembler(void const *Decoder) { |
| 185 | return *static_cast<HexagonDisassembler const *>(Decoder); |
| 186 | } |
| 187 | MCContext &contextFromDecoder(void const *Decoder) { |
| 188 | return disassembler(Decoder).getContext(); |
| 189 | } |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | DecodeStatus HexagonDisassembler::getSingleInstruction( |
| 193 | MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, |
| 194 | raw_ostream &os, raw_ostream &cs, bool &Complete) const { |
| 195 | assert(Bytes.size() >= HEXAGON_INSTR_SIZE); |
| 196 | |
| 197 | uint32_t Instruction = |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 198 | (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 199 | |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 200 | auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); |
| 201 | if ((Instruction & HexagonII::INST_PARSE_MASK) == |
| 202 | HexagonII::INST_PARSE_LOOP_END) { |
| 203 | if (BundleSize == 0) |
| 204 | HexagonMCInstrInfo::setInnerLoop(MCB); |
| 205 | else if (BundleSize == 1) |
| 206 | HexagonMCInstrInfo::setOuterLoop(MCB); |
| 207 | else |
| 208 | return DecodeStatus::Fail; |
| 209 | } |
| 210 | |
| 211 | DecodeStatus Result = DecodeStatus::Success; |
| 212 | if ((Instruction & HexagonII::INST_PARSE_MASK) == |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 213 | HexagonII::INST_PARSE_DUPLEX) { |
| 214 | // Determine the instruction class of each instruction in the duplex. |
| 215 | unsigned duplexIClass, IClassLow, IClassHigh; |
| 216 | |
| 217 | duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); |
| 218 | switch (duplexIClass) { |
| 219 | default: |
| 220 | return MCDisassembler::Fail; |
| 221 | case 0: |
| 222 | IClassLow = HexagonII::HSIG_L1; |
| 223 | IClassHigh = HexagonII::HSIG_L1; |
| 224 | break; |
| 225 | case 1: |
| 226 | IClassLow = HexagonII::HSIG_L2; |
| 227 | IClassHigh = HexagonII::HSIG_L1; |
| 228 | break; |
| 229 | case 2: |
| 230 | IClassLow = HexagonII::HSIG_L2; |
| 231 | IClassHigh = HexagonII::HSIG_L2; |
| 232 | break; |
| 233 | case 3: |
| 234 | IClassLow = HexagonII::HSIG_A; |
| 235 | IClassHigh = HexagonII::HSIG_A; |
| 236 | break; |
| 237 | case 4: |
| 238 | IClassLow = HexagonII::HSIG_L1; |
| 239 | IClassHigh = HexagonII::HSIG_A; |
| 240 | break; |
| 241 | case 5: |
| 242 | IClassLow = HexagonII::HSIG_L2; |
| 243 | IClassHigh = HexagonII::HSIG_A; |
| 244 | break; |
| 245 | case 6: |
| 246 | IClassLow = HexagonII::HSIG_S1; |
| 247 | IClassHigh = HexagonII::HSIG_A; |
| 248 | break; |
| 249 | case 7: |
| 250 | IClassLow = HexagonII::HSIG_S2; |
| 251 | IClassHigh = HexagonII::HSIG_A; |
| 252 | break; |
| 253 | case 8: |
| 254 | IClassLow = HexagonII::HSIG_S1; |
| 255 | IClassHigh = HexagonII::HSIG_L1; |
| 256 | break; |
| 257 | case 9: |
| 258 | IClassLow = HexagonII::HSIG_S1; |
| 259 | IClassHigh = HexagonII::HSIG_L2; |
| 260 | break; |
| 261 | case 10: |
| 262 | IClassLow = HexagonII::HSIG_S1; |
| 263 | IClassHigh = HexagonII::HSIG_S1; |
| 264 | break; |
| 265 | case 11: |
| 266 | IClassLow = HexagonII::HSIG_S2; |
| 267 | IClassHigh = HexagonII::HSIG_S1; |
| 268 | break; |
| 269 | case 12: |
| 270 | IClassLow = HexagonII::HSIG_S2; |
| 271 | IClassHigh = HexagonII::HSIG_L1; |
| 272 | break; |
| 273 | case 13: |
| 274 | IClassLow = HexagonII::HSIG_S2; |
| 275 | IClassHigh = HexagonII::HSIG_L2; |
| 276 | break; |
| 277 | case 14: |
| 278 | IClassLow = HexagonII::HSIG_S2; |
| 279 | IClassHigh = HexagonII::HSIG_S2; |
| 280 | break; |
| 281 | } |
| 282 | |
| 283 | // Set the MCInst to be a duplex instruction. Which one doesn't matter. |
| 284 | MI.setOpcode(Hexagon::DuplexIClass0); |
| 285 | |
| 286 | // Decode each instruction in the duplex. |
| 287 | // Create an MCInst for each instruction. |
| 288 | unsigned instLow = Instruction & 0x1fff; |
| 289 | unsigned instHigh = (Instruction >> 16) & 0x1fff; |
| 290 | unsigned opLow; |
| 291 | if (GetSubinstOpcode(IClassLow, instLow, opLow, os) != |
| 292 | MCDisassembler::Success) |
| 293 | return MCDisassembler::Fail; |
| 294 | unsigned opHigh; |
| 295 | if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) != |
| 296 | MCDisassembler::Success) |
| 297 | return MCDisassembler::Fail; |
| 298 | MCInst *MILow = new (getContext()) MCInst; |
| 299 | MILow->setOpcode(opLow); |
| 300 | MCInst *MIHigh = new (getContext()) MCInst; |
| 301 | MIHigh->setOpcode(opHigh); |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 302 | addSubinstOperands(MILow, opLow, instLow); |
| 303 | addSubinstOperands(MIHigh, opHigh, instHigh); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 304 | // see ConvertToSubInst() in |
| 305 | // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp |
| 306 | |
| 307 | // Add the duplex instruction MCInsts as operands to the passed in MCInst. |
| 308 | MCOperand OPLow = MCOperand::createInst(MILow); |
| 309 | MCOperand OPHigh = MCOperand::createInst(MIHigh); |
| 310 | MI.addOperand(OPLow); |
| 311 | MI.addOperand(OPHigh); |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 312 | Complete = true; |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 313 | } else { |
| 314 | if ((Instruction & HexagonII::INST_PARSE_MASK) == |
| 315 | HexagonII::INST_PARSE_PACKET_END) |
| 316 | Complete = true; |
| 317 | // Calling the auto-generated decoder function. |
| 318 | Result = |
| 319 | decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 320 | |
| 321 | // If a, "standard" insn isn't found check special cases. |
| 322 | if (MCDisassembler::Success != Result || |
| 323 | MI.getOpcode() == Hexagon::A4_ext) { |
| 324 | Result = decodeImmext(MI, Instruction, this); |
| 325 | if (MCDisassembler::Success != Result) { |
| 326 | Result = decodeSpecial(MI, Instruction); |
| 327 | } |
| 328 | } else { |
| 329 | // If the instruction is a compound instruction, register values will |
| 330 | // follow the duplex model, so the register values in the MCInst are |
| 331 | // incorrect. If the instruction is a compound, loop through the |
| 332 | // operands and change registers appropriately. |
| 333 | if (llvm::HexagonMCInstrInfo::getType(*MCII, MI) == |
| 334 | HexagonII::TypeCOMPOUND) { |
| 335 | for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) { |
| 336 | if (i->isReg()) { |
| 337 | unsigned reg = i->getReg() - Hexagon::R0; |
| 338 | i->setReg(getRegFromSubinstEncoding(reg)); |
| 339 | } |
| 340 | } |
| 341 | } |
| 342 | } |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 343 | } |
Colin LeMahieu | 68d967d | 2015-05-29 14:44:13 +0000 | [diff] [blame] | 344 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 345 | if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { |
| 346 | unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); |
| 347 | MCOperand &MCO = MI.getOperand(OpIndex); |
| 348 | assert(MCO.isReg() && "New value consumers must be registers"); |
| 349 | unsigned Register = |
| 350 | getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); |
| 351 | if ((Register & 0x6) == 0) |
| 352 | // HexagonPRM 10.11 Bit 1-2 == 0 is reserved |
| 353 | return MCDisassembler::Fail; |
| 354 | unsigned Lookback = (Register & 0x6) >> 1; |
| 355 | unsigned Offset = 1; |
| 356 | bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); |
| 357 | auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); |
| 358 | auto i = Instructions.end() - 1; |
| 359 | for (auto n = Instructions.begin() - 1;; --i, ++Offset) { |
| 360 | if (i == n) |
| 361 | // Couldn't find producer |
| 362 | return MCDisassembler::Fail; |
| 363 | if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) |
| 364 | // Skip scalars when calculating distances for vectors |
| 365 | ++Lookback; |
| 366 | if (HexagonMCInstrInfo::isImmext(*i->getInst())) |
| 367 | ++Lookback; |
| 368 | if (Offset == Lookback) |
| 369 | break; |
| 370 | } |
| 371 | auto const &Inst = *i->getInst(); |
| 372 | bool SubregBit = (Register & 0x1) != 0; |
| 373 | if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { |
| 374 | // If subreg bit is set we're selecting the second produced newvalue |
| 375 | unsigned Producer = |
| 376 | HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); |
| 377 | assert(Producer != Hexagon::NoRegister); |
| 378 | MCO.setReg(Producer); |
| 379 | } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { |
| 380 | unsigned Producer = |
| 381 | HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); |
| 382 | if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) |
| 383 | Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; |
| 384 | else if (SubregBit) |
| 385 | // Subreg bit should not be set for non-doublevector newvalue producers |
| 386 | return MCDisassembler::Fail; |
| 387 | assert(Producer != Hexagon::NoRegister); |
| 388 | MCO.setReg(Producer); |
| 389 | } else |
| 390 | return MCDisassembler::Fail; |
| 391 | } |
| 392 | |
| 393 | adjustExtendedInstructions(MI, MCB); |
| 394 | MCInst const *Extender = |
| 395 | HexagonMCInstrInfo::extenderForIndex(MCB, |
| 396 | HexagonMCInstrInfo::bundleSize(MCB)); |
| 397 | if(Extender != nullptr) { |
| 398 | MCInst const & Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ? |
| 399 | *MI.getOperand(1).getInst() : MI; |
| 400 | if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && |
| 401 | !HexagonMCInstrInfo::isExtended(*MCII, Inst)) |
| 402 | return MCDisassembler::Fail; |
| 403 | } |
Colin LeMahieu | 5d6f03b | 2014-12-04 03:41:21 +0000 | [diff] [blame] | 404 | return Result; |
NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame] | 405 | } |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 406 | |
| 407 | void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI, |
| 408 | MCInst const &MCB) const { |
| 409 | if (!HexagonMCInstrInfo::hasExtenderForIndex( |
| 410 | MCB, HexagonMCInstrInfo::bundleSize(MCB))) { |
| 411 | unsigned opcode; |
| 412 | // This code is used by the disassembler to disambiguate between GP |
| 413 | // relative and absolute addressing instructions since they both have |
| 414 | // same encoding bits. However, an absolute addressing instruction must |
| 415 | // follow an immediate extender. Disassembler alwaus select absolute |
| 416 | // addressing instructions first and uses this code to change them into |
| 417 | // GP relative instruction in the absence of the corresponding immediate |
| 418 | // extender. |
| 419 | switch (MCI.getOpcode()) { |
| 420 | case Hexagon::S2_storerbabs: |
| 421 | opcode = Hexagon::S2_storerbgp; |
| 422 | break; |
| 423 | case Hexagon::S2_storerhabs: |
| 424 | opcode = Hexagon::S2_storerhgp; |
| 425 | break; |
| 426 | case Hexagon::S2_storerfabs: |
| 427 | opcode = Hexagon::S2_storerfgp; |
| 428 | break; |
| 429 | case Hexagon::S2_storeriabs: |
| 430 | opcode = Hexagon::S2_storerigp; |
| 431 | break; |
| 432 | case Hexagon::S2_storerbnewabs: |
| 433 | opcode = Hexagon::S2_storerbnewgp; |
| 434 | break; |
| 435 | case Hexagon::S2_storerhnewabs: |
| 436 | opcode = Hexagon::S2_storerhnewgp; |
| 437 | break; |
| 438 | case Hexagon::S2_storerinewabs: |
| 439 | opcode = Hexagon::S2_storerinewgp; |
| 440 | break; |
| 441 | case Hexagon::S2_storerdabs: |
| 442 | opcode = Hexagon::S2_storerdgp; |
| 443 | break; |
| 444 | case Hexagon::L4_loadrb_abs: |
| 445 | opcode = Hexagon::L2_loadrbgp; |
| 446 | break; |
| 447 | case Hexagon::L4_loadrub_abs: |
| 448 | opcode = Hexagon::L2_loadrubgp; |
| 449 | break; |
| 450 | case Hexagon::L4_loadrh_abs: |
| 451 | opcode = Hexagon::L2_loadrhgp; |
| 452 | break; |
| 453 | case Hexagon::L4_loadruh_abs: |
| 454 | opcode = Hexagon::L2_loadruhgp; |
| 455 | break; |
| 456 | case Hexagon::L4_loadri_abs: |
| 457 | opcode = Hexagon::L2_loadrigp; |
| 458 | break; |
| 459 | case Hexagon::L4_loadrd_abs: |
| 460 | opcode = Hexagon::L2_loadrdgp; |
| 461 | break; |
| 462 | default: |
| 463 | opcode = MCI.getOpcode(); |
| 464 | } |
| 465 | MCI.setOpcode(opcode); |
| 466 | } |
| 467 | } |
| 468 | |
| 469 | namespace llvm { |
| 470 | extern const MCInstrDesc HexagonInsts[]; |
| 471 | } |
| 472 | |
| 473 | static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, |
| 474 | const uint16_t Table[], size_t Size) { |
| 475 | if (RegNo < Size) { |
| 476 | Inst.addOperand(MCOperand::createReg(Table[RegNo])); |
| 477 | return MCDisassembler::Success; |
| 478 | } else |
| 479 | return MCDisassembler::Fail; |
| 480 | } |
| 481 | |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 482 | static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, |
| 483 | uint64_t Address, |
| 484 | const void *Decoder) { |
| 485 | return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); |
| 486 | } |
| 487 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 488 | static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 489 | uint64_t Address, |
| 490 | const void *Decoder) { |
| 491 | static const uint16_t IntRegDecoderTable[] = { |
| 492 | Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, |
| 493 | Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, |
| 494 | Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, |
| 495 | Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, |
| 496 | Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, |
| 497 | Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, |
| 498 | Hexagon::R30, Hexagon::R31}; |
| 499 | |
| 500 | return (DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable, |
| 501 | sizeof(IntRegDecoderTable))); |
| 502 | } |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 503 | |
| 504 | static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 505 | uint64_t /*Address*/, |
| 506 | const void *Decoder) { |
| 507 | static const uint16_t VecRegDecoderTable[] = { |
| 508 | Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, |
| 509 | Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, |
| 510 | Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, |
| 511 | Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, |
| 512 | Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, |
| 513 | Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, |
| 514 | Hexagon::V30, Hexagon::V31}; |
| 515 | |
| 516 | return (DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable, |
| 517 | sizeof(VecRegDecoderTable))); |
| 518 | } |
| 519 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 520 | static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 521 | uint64_t /*Address*/, |
| 522 | const void *Decoder) { |
| 523 | static const uint16_t DoubleRegDecoderTable[] = { |
| 524 | Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, |
| 525 | Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, |
| 526 | Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, |
| 527 | Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; |
| 528 | |
| 529 | return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable, |
| 530 | sizeof(DoubleRegDecoderTable))); |
| 531 | } |
| 532 | |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 533 | static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 534 | uint64_t /*Address*/, |
| 535 | const void *Decoder) { |
| 536 | static const uint16_t VecDblRegDecoderTable[] = { |
| 537 | Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, |
| 538 | Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, |
| 539 | Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, |
| 540 | Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; |
| 541 | |
| 542 | return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable, |
| 543 | sizeof(VecDblRegDecoderTable))); |
| 544 | } |
| 545 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 546 | static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 547 | uint64_t /*Address*/, |
| 548 | const void *Decoder) { |
| 549 | static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, |
| 550 | Hexagon::P2, Hexagon::P3}; |
| 551 | |
| 552 | return (DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable, |
| 553 | sizeof(PredRegDecoderTable))); |
| 554 | } |
| 555 | |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 556 | static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 557 | uint64_t /*Address*/, |
| 558 | const void *Decoder) { |
| 559 | static const uint16_t VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, |
| 560 | Hexagon::Q2, Hexagon::Q3}; |
| 561 | |
| 562 | return (DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable, |
| 563 | sizeof(VecPredRegDecoderTable))); |
| 564 | } |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 565 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 566 | static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 567 | uint64_t /*Address*/, |
| 568 | const void *Decoder) { |
| 569 | static const uint16_t CtrlRegDecoderTable[] = { |
| 570 | Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, |
| 571 | Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7, |
| 572 | Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, |
| 573 | Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC |
| 574 | }; |
| 575 | |
| 576 | if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0])) |
| 577 | return MCDisassembler::Fail; |
| 578 | |
| 579 | if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister) |
| 580 | return MCDisassembler::Fail; |
| 581 | |
| 582 | unsigned Register = CtrlRegDecoderTable[RegNo]; |
| 583 | Inst.addOperand(MCOperand::createReg(Register)); |
| 584 | return MCDisassembler::Success; |
| 585 | } |
| 586 | |
| 587 | static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, |
| 588 | uint64_t /*Address*/, |
| 589 | const void *Decoder) { |
| 590 | static const uint16_t CtrlReg64DecoderTable[] = { |
| 591 | Hexagon::C1_0, Hexagon::NoRegister, |
| 592 | Hexagon::C3_2, Hexagon::NoRegister, |
| 593 | Hexagon::C7_6, Hexagon::NoRegister, |
| 594 | Hexagon::C9_8, Hexagon::NoRegister, |
| 595 | Hexagon::C11_10, Hexagon::NoRegister, |
| 596 | Hexagon::CS, Hexagon::NoRegister, |
| 597 | Hexagon::UPC, Hexagon::NoRegister |
| 598 | }; |
| 599 | |
| 600 | if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0])) |
| 601 | return MCDisassembler::Fail; |
| 602 | |
| 603 | if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister) |
| 604 | return MCDisassembler::Fail; |
| 605 | |
| 606 | unsigned Register = CtrlReg64DecoderTable[RegNo]; |
| 607 | Inst.addOperand(MCOperand::createReg(Register)); |
| 608 | return MCDisassembler::Success; |
| 609 | } |
| 610 | |
| 611 | static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 612 | uint64_t /*Address*/, |
| 613 | const void *Decoder) { |
| 614 | unsigned Register = 0; |
| 615 | switch (RegNo) { |
| 616 | case 0: |
| 617 | Register = Hexagon::M0; |
| 618 | break; |
| 619 | case 1: |
| 620 | Register = Hexagon::M1; |
| 621 | break; |
| 622 | default: |
| 623 | return MCDisassembler::Fail; |
| 624 | } |
| 625 | Inst.addOperand(MCOperand::createReg(Register)); |
| 626 | return MCDisassembler::Success; |
| 627 | } |
| 628 | |
| 629 | namespace { |
| 630 | uint32_t fullValue(MCInstrInfo const &MCII, |
| 631 | MCInst &MCB, |
| 632 | MCInst &MI, |
| 633 | int64_t Value) { |
| 634 | MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( |
| 635 | MCB, HexagonMCInstrInfo::bundleSize(MCB)); |
| 636 | if(!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) |
| 637 | return Value; |
| 638 | unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); |
| 639 | uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; |
| 640 | int64_t Bits; |
| 641 | bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); |
| 642 | assert(Success);(void)Success; |
| 643 | uint32_t Upper26 = static_cast<uint32_t>(Bits); |
| 644 | uint32_t Operand = Upper26 | Lower6; |
| 645 | return Operand; |
| 646 | } |
| 647 | template <size_t T> |
| 648 | void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { |
| 649 | HexagonDisassembler const &Disassembler = disassembler(Decoder); |
| 650 | int64_t FullValue = fullValue(*Disassembler.MCII, |
| 651 | **Disassembler.CurrentBundle, |
| 652 | MI, SignExtend64<T>(tmp)); |
| 653 | int64_t Extended = SignExtend64<32>(FullValue); |
| 654 | HexagonMCInstrInfo::addConstant(MI, Extended, |
| 655 | Disassembler.getContext()); |
| 656 | } |
| 657 | } |
| 658 | |
| 659 | static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, |
| 660 | uint64_t /*Address*/, |
| 661 | const void *Decoder) { |
| 662 | HexagonDisassembler const &Disassembler = disassembler(Decoder); |
| 663 | int64_t FullValue = fullValue(*Disassembler.MCII, |
| 664 | **Disassembler.CurrentBundle, |
| 665 | MI, tmp); |
| 666 | assert(FullValue >= 0 && "Negative in unsigned decoder"); |
| 667 | HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); |
| 668 | return MCDisassembler::Success; |
| 669 | } |
| 670 | |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 671 | static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, |
| 672 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 673 | signedDecoder<16>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 674 | return MCDisassembler::Success; |
| 675 | } |
| 676 | |
| 677 | static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, |
| 678 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 679 | signedDecoder<12>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 680 | return MCDisassembler::Success; |
| 681 | } |
| 682 | |
| 683 | static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, |
| 684 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 685 | signedDecoder<11>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 686 | return MCDisassembler::Success; |
| 687 | } |
| 688 | |
| 689 | static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, |
| 690 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 691 | HexagonMCInstrInfo::addConstant(MI, SignExtend64<12>(tmp), contextFromDecoder(Decoder)); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 692 | return MCDisassembler::Success; |
| 693 | } |
| 694 | |
| 695 | static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, |
| 696 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 697 | signedDecoder<13>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 698 | return MCDisassembler::Success; |
| 699 | } |
| 700 | |
| 701 | static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, |
| 702 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 703 | signedDecoder<14>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 704 | return MCDisassembler::Success; |
| 705 | } |
| 706 | |
| 707 | static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, |
| 708 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 709 | signedDecoder<10>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 710 | return MCDisassembler::Success; |
| 711 | } |
| 712 | |
| 713 | static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, |
| 714 | const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 715 | signedDecoder<8>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 716 | return MCDisassembler::Success; |
| 717 | } |
| 718 | |
| 719 | static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, |
| 720 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 721 | signedDecoder<6>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 722 | return MCDisassembler::Success; |
| 723 | } |
| 724 | |
| 725 | static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, |
| 726 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 727 | signedDecoder<4>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 728 | return MCDisassembler::Success; |
| 729 | } |
| 730 | |
| 731 | static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, |
| 732 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 733 | signedDecoder<5>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 734 | return MCDisassembler::Success; |
| 735 | } |
| 736 | |
| 737 | static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, |
| 738 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 739 | signedDecoder<6>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 740 | return MCDisassembler::Success; |
| 741 | } |
| 742 | |
| 743 | static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, |
| 744 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 745 | signedDecoder<7>(MI, tmp, Decoder); |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 746 | return MCDisassembler::Success; |
| 747 | } |
| 748 | |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 749 | static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, |
| 750 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 751 | signedDecoder<10>(MI, tmp, Decoder); |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 752 | return MCDisassembler::Success; |
| 753 | } |
| 754 | |
| 755 | static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, |
| 756 | uint64_t /*Address*/, const void *Decoder) { |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 757 | signedDecoder<19>(MI, tmp, Decoder); |
Colin LeMahieu | 7c95871 | 2015-10-17 01:33:04 +0000 | [diff] [blame] | 758 | return MCDisassembler::Success; |
| 759 | } |
| 760 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 761 | // custom decoder for various jump/call immediates |
| 762 | static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, |
| 763 | const void *Decoder) { |
| 764 | HexagonDisassembler const &Disassembler = disassembler(Decoder); |
| 765 | unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); |
| 766 | // r13_2 is not extendable, so if there are no extent bits, it's r13_2 |
| 767 | if (Bits == 0) |
| 768 | Bits = 15; |
| 769 | uint32_t FullValue = fullValue(*Disassembler.MCII, |
| 770 | **Disassembler.CurrentBundle, |
| 771 | MI, SignExtend64(tmp, Bits)); |
| 772 | int64_t Extended = SignExtend64<32>(FullValue) + Address; |
| 773 | if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, |
| 774 | 0, 4)) |
| 775 | HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); |
| 776 | return MCDisassembler::Success; |
| 777 | } |
| 778 | |
| 779 | // Addressing mode dependent load store opcode map. |
| 780 | // - If an insn is preceded by an extender the address is absolute. |
| 781 | // - memw(##symbol) = r0 |
| 782 | // - If an insn is not preceded by an extender the address is GP relative. |
| 783 | // - memw(gp + #symbol) = r0 |
| 784 | // Please note that the instructions must be ordered in the descending order |
| 785 | // of their opcode. |
| 786 | // HexagonII::INST_ICLASS_ST |
| 787 | static unsigned int StoreConditionalOpcodeData[][2] = { |
| 788 | {S4_pstorerdfnew_abs, 0xafc02084}, |
| 789 | {S4_pstorerdtnew_abs, 0xafc02080}, |
| 790 | {S4_pstorerdf_abs, 0xafc00084}, |
| 791 | {S4_pstorerdt_abs, 0xafc00080}, |
| 792 | {S4_pstorerinewfnew_abs, 0xafa03084}, |
| 793 | {S4_pstorerinewtnew_abs, 0xafa03080}, |
| 794 | {S4_pstorerhnewfnew_abs, 0xafa02884}, |
| 795 | {S4_pstorerhnewtnew_abs, 0xafa02880}, |
| 796 | {S4_pstorerbnewfnew_abs, 0xafa02084}, |
| 797 | {S4_pstorerbnewtnew_abs, 0xafa02080}, |
| 798 | {S4_pstorerinewf_abs, 0xafa01084}, |
| 799 | {S4_pstorerinewt_abs, 0xafa01080}, |
| 800 | {S4_pstorerhnewf_abs, 0xafa00884}, |
| 801 | {S4_pstorerhnewt_abs, 0xafa00880}, |
| 802 | {S4_pstorerbnewf_abs, 0xafa00084}, |
| 803 | {S4_pstorerbnewt_abs, 0xafa00080}, |
| 804 | {S4_pstorerifnew_abs, 0xaf802084}, |
| 805 | {S4_pstoreritnew_abs, 0xaf802080}, |
| 806 | {S4_pstorerif_abs, 0xaf800084}, |
| 807 | {S4_pstorerit_abs, 0xaf800080}, |
| 808 | {S4_pstorerhfnew_abs, 0xaf402084}, |
| 809 | {S4_pstorerhtnew_abs, 0xaf402080}, |
| 810 | {S4_pstorerhf_abs, 0xaf400084}, |
| 811 | {S4_pstorerht_abs, 0xaf400080}, |
| 812 | {S4_pstorerbfnew_abs, 0xaf002084}, |
| 813 | {S4_pstorerbtnew_abs, 0xaf002080}, |
| 814 | {S4_pstorerbf_abs, 0xaf000084}, |
| 815 | {S4_pstorerbt_abs, 0xaf000080}}; |
| 816 | // HexagonII::INST_ICLASS_LD |
| 817 | |
| 818 | // HexagonII::INST_ICLASS_LD_ST_2 |
| 819 | static unsigned int LoadStoreOpcodeData[][2] = {{L4_loadrd_abs, 0x49c00000}, |
| 820 | {L4_loadri_abs, 0x49800000}, |
| 821 | {L4_loadruh_abs, 0x49600000}, |
| 822 | {L4_loadrh_abs, 0x49400000}, |
| 823 | {L4_loadrub_abs, 0x49200000}, |
| 824 | {L4_loadrb_abs, 0x49000000}, |
| 825 | {S2_storerdabs, 0x48c00000}, |
| 826 | {S2_storerinewabs, 0x48a01000}, |
| 827 | {S2_storerhnewabs, 0x48a00800}, |
| 828 | {S2_storerbnewabs, 0x48a00000}, |
| 829 | {S2_storeriabs, 0x48800000}, |
| 830 | {S2_storerfabs, 0x48600000}, |
| 831 | {S2_storerhabs, 0x48400000}, |
| 832 | {S2_storerbabs, 0x48000000}}; |
| 833 | static int NumCondS = |
| 834 | sizeof(StoreConditionalOpcodeData) / sizeof(StoreConditionalOpcodeData[0]); |
| 835 | static int NumLS = sizeof(LoadStoreOpcodeData) / sizeof(LoadStoreOpcodeData[0]); |
| 836 | |
| 837 | static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) { |
| 838 | |
| 839 | unsigned MachineOpcode = 0; |
| 840 | unsigned LLVMOpcode = 0; |
| 841 | int i; |
| 842 | |
| 843 | if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_ST) { |
| 844 | for (i = 0; i < NumCondS; ++i) { |
| 845 | if ((insn & StoreConditionalOpcodeData[i][1]) == |
| 846 | StoreConditionalOpcodeData[i][1]) { |
| 847 | MachineOpcode = StoreConditionalOpcodeData[i][1]; |
| 848 | LLVMOpcode = StoreConditionalOpcodeData[i][0]; |
| 849 | break; |
| 850 | } |
| 851 | } |
| 852 | } |
| 853 | if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_LD_ST_2) { |
| 854 | for (i = 0; i < NumLS; ++i) { |
| 855 | if ((insn & LoadStoreOpcodeData[i][1]) == LoadStoreOpcodeData[i][1]) { |
| 856 | MachineOpcode = LoadStoreOpcodeData[i][1]; |
| 857 | LLVMOpcode = LoadStoreOpcodeData[i][0]; |
| 858 | break; |
| 859 | } |
| 860 | } |
| 861 | } |
| 862 | |
| 863 | if (MachineOpcode) { |
| 864 | unsigned Value = 0; |
| 865 | unsigned shift = 0; |
| 866 | MI.setOpcode(LLVMOpcode); |
| 867 | // Remove the parse bits from the insn. |
| 868 | insn &= ~HexagonII::INST_PARSE_MASK; |
| 869 | |
| 870 | switch (LLVMOpcode) { |
| 871 | default: |
| 872 | return MCDisassembler::Fail; |
| 873 | break; |
| 874 | |
| 875 | case Hexagon::S4_pstorerdf_abs: |
| 876 | case Hexagon::S4_pstorerdt_abs: |
| 877 | case Hexagon::S4_pstorerdfnew_abs: |
| 878 | case Hexagon::S4_pstorerdtnew_abs: { |
| 879 | // op: Pv |
| 880 | Value = insn & UINT64_C(3); |
| 881 | DecodePredRegsRegisterClass(MI, Value, 0, 0); |
| 882 | // op: u6 |
| 883 | Value = (insn >> 12) & UINT64_C(48); |
| 884 | Value |= (insn >> 3) & UINT64_C(15); |
| 885 | MI.addOperand(MCOperand::createImm(Value)); |
| 886 | // op: Rtt |
| 887 | Value = (insn >> 8) & UINT64_C(31); |
| 888 | DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); |
| 889 | break; |
| 890 | } |
| 891 | |
| 892 | case Hexagon::S4_pstorerbnewf_abs: |
| 893 | case Hexagon::S4_pstorerbnewt_abs: |
| 894 | case Hexagon::S4_pstorerbnewfnew_abs: |
| 895 | case Hexagon::S4_pstorerbnewtnew_abs: |
| 896 | case Hexagon::S4_pstorerhnewf_abs: |
| 897 | case Hexagon::S4_pstorerhnewt_abs: |
| 898 | case Hexagon::S4_pstorerhnewfnew_abs: |
| 899 | case Hexagon::S4_pstorerhnewtnew_abs: |
| 900 | case Hexagon::S4_pstorerinewf_abs: |
| 901 | case Hexagon::S4_pstorerinewt_abs: |
| 902 | case Hexagon::S4_pstorerinewfnew_abs: |
| 903 | case Hexagon::S4_pstorerinewtnew_abs: { |
| 904 | // op: Pv |
| 905 | Value = insn & UINT64_C(3); |
| 906 | DecodePredRegsRegisterClass(MI, Value, 0, 0); |
| 907 | // op: u6 |
| 908 | Value = (insn >> 12) & UINT64_C(48); |
| 909 | Value |= (insn >> 3) & UINT64_C(15); |
| 910 | MI.addOperand(MCOperand::createImm(Value)); |
| 911 | // op: Nt |
| 912 | Value = (insn >> 8) & UINT64_C(7); |
| 913 | DecodeIntRegsRegisterClass(MI, Value, 0, 0); |
| 914 | break; |
| 915 | } |
| 916 | |
| 917 | case Hexagon::S4_pstorerbf_abs: |
| 918 | case Hexagon::S4_pstorerbt_abs: |
| 919 | case Hexagon::S4_pstorerbfnew_abs: |
| 920 | case Hexagon::S4_pstorerbtnew_abs: |
| 921 | case Hexagon::S4_pstorerhf_abs: |
| 922 | case Hexagon::S4_pstorerht_abs: |
| 923 | case Hexagon::S4_pstorerhfnew_abs: |
| 924 | case Hexagon::S4_pstorerhtnew_abs: |
| 925 | case Hexagon::S4_pstorerif_abs: |
| 926 | case Hexagon::S4_pstorerit_abs: |
| 927 | case Hexagon::S4_pstorerifnew_abs: |
| 928 | case Hexagon::S4_pstoreritnew_abs: { |
| 929 | // op: Pv |
| 930 | Value = insn & UINT64_C(3); |
| 931 | DecodePredRegsRegisterClass(MI, Value, 0, 0); |
| 932 | // op: u6 |
| 933 | Value = (insn >> 12) & UINT64_C(48); |
| 934 | Value |= (insn >> 3) & UINT64_C(15); |
| 935 | MI.addOperand(MCOperand::createImm(Value)); |
| 936 | // op: Rt |
| 937 | Value = (insn >> 8) & UINT64_C(31); |
| 938 | DecodeIntRegsRegisterClass(MI, Value, 0, 0); |
| 939 | break; |
| 940 | } |
| 941 | |
| 942 | case Hexagon::L4_ploadrdf_abs: |
| 943 | case Hexagon::L4_ploadrdt_abs: |
| 944 | case Hexagon::L4_ploadrdfnew_abs: |
| 945 | case Hexagon::L4_ploadrdtnew_abs: { |
| 946 | // op: Rdd |
| 947 | Value = insn & UINT64_C(31); |
| 948 | DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); |
| 949 | // op: Pt |
| 950 | Value = ((insn >> 9) & UINT64_C(3)); |
| 951 | DecodePredRegsRegisterClass(MI, Value, 0, 0); |
| 952 | // op: u6 |
| 953 | Value = ((insn >> 15) & UINT64_C(62)); |
| 954 | Value |= ((insn >> 8) & UINT64_C(1)); |
| 955 | MI.addOperand(MCOperand::createImm(Value)); |
| 956 | break; |
| 957 | } |
| 958 | |
| 959 | case Hexagon::L4_ploadrbf_abs: |
| 960 | case Hexagon::L4_ploadrbt_abs: |
| 961 | case Hexagon::L4_ploadrbfnew_abs: |
| 962 | case Hexagon::L4_ploadrbtnew_abs: |
| 963 | case Hexagon::L4_ploadrhf_abs: |
| 964 | case Hexagon::L4_ploadrht_abs: |
| 965 | case Hexagon::L4_ploadrhfnew_abs: |
| 966 | case Hexagon::L4_ploadrhtnew_abs: |
| 967 | case Hexagon::L4_ploadrubf_abs: |
| 968 | case Hexagon::L4_ploadrubt_abs: |
| 969 | case Hexagon::L4_ploadrubfnew_abs: |
| 970 | case Hexagon::L4_ploadrubtnew_abs: |
| 971 | case Hexagon::L4_ploadruhf_abs: |
| 972 | case Hexagon::L4_ploadruht_abs: |
| 973 | case Hexagon::L4_ploadruhfnew_abs: |
| 974 | case Hexagon::L4_ploadruhtnew_abs: |
| 975 | case Hexagon::L4_ploadrif_abs: |
| 976 | case Hexagon::L4_ploadrit_abs: |
| 977 | case Hexagon::L4_ploadrifnew_abs: |
| 978 | case Hexagon::L4_ploadritnew_abs: |
| 979 | // op: Rd |
| 980 | Value = insn & UINT64_C(31); |
| 981 | DecodeIntRegsRegisterClass(MI, Value, 0, 0); |
| 982 | // op: Pt |
| 983 | Value = (insn >> 9) & UINT64_C(3); |
| 984 | DecodePredRegsRegisterClass(MI, Value, 0, 0); |
| 985 | // op: u6 |
| 986 | Value = (insn >> 15) & UINT64_C(62); |
| 987 | Value |= (insn >> 8) & UINT64_C(1); |
| 988 | MI.addOperand(MCOperand::createImm(Value)); |
| 989 | break; |
| 990 | |
| 991 | // op: g16_2 |
| 992 | case (Hexagon::L4_loadri_abs): |
| 993 | ++shift; |
| 994 | // op: g16_1 |
| 995 | case Hexagon::L4_loadrh_abs: |
| 996 | case Hexagon::L4_loadruh_abs: |
| 997 | ++shift; |
| 998 | // op: g16_0 |
| 999 | case Hexagon::L4_loadrb_abs: |
| 1000 | case Hexagon::L4_loadrub_abs: { |
| 1001 | // op: Rd |
| 1002 | Value |= insn & UINT64_C(31); |
| 1003 | DecodeIntRegsRegisterClass(MI, Value, 0, 0); |
| 1004 | Value = (insn >> 11) & UINT64_C(49152); |
| 1005 | Value |= (insn >> 7) & UINT64_C(15872); |
| 1006 | Value |= (insn >> 5) & UINT64_C(511); |
| 1007 | MI.addOperand(MCOperand::createImm(Value << shift)); |
| 1008 | break; |
| 1009 | } |
| 1010 | |
| 1011 | case Hexagon::L4_loadrd_abs: { |
| 1012 | Value = insn & UINT64_C(31); |
| 1013 | DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); |
| 1014 | Value = (insn >> 11) & UINT64_C(49152); |
| 1015 | Value |= (insn >> 7) & UINT64_C(15872); |
| 1016 | Value |= (insn >> 5) & UINT64_C(511); |
| 1017 | MI.addOperand(MCOperand::createImm(Value << 3)); |
| 1018 | break; |
| 1019 | } |
| 1020 | |
| 1021 | case Hexagon::S2_storerdabs: { |
| 1022 | // op: g16_3 |
| 1023 | Value = (insn >> 11) & UINT64_C(49152); |
| 1024 | Value |= (insn >> 7) & UINT64_C(15872); |
| 1025 | Value |= (insn >> 5) & UINT64_C(256); |
| 1026 | Value |= insn & UINT64_C(255); |
| 1027 | MI.addOperand(MCOperand::createImm(Value << 3)); |
| 1028 | // op: Rtt |
| 1029 | Value = (insn >> 8) & UINT64_C(31); |
| 1030 | DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); |
| 1031 | break; |
| 1032 | } |
| 1033 | |
| 1034 | // op: g16_2 |
| 1035 | case Hexagon::S2_storerinewabs: |
| 1036 | ++shift; |
| 1037 | // op: g16_1 |
| 1038 | case Hexagon::S2_storerhnewabs: |
| 1039 | ++shift; |
| 1040 | // op: g16_0 |
| 1041 | case Hexagon::S2_storerbnewabs: { |
| 1042 | Value = (insn >> 11) & UINT64_C(49152); |
| 1043 | Value |= (insn >> 7) & UINT64_C(15872); |
| 1044 | Value |= (insn >> 5) & UINT64_C(256); |
| 1045 | Value |= insn & UINT64_C(255); |
| 1046 | MI.addOperand(MCOperand::createImm(Value << shift)); |
| 1047 | // op: Nt |
| 1048 | Value = (insn >> 8) & UINT64_C(7); |
| 1049 | DecodeIntRegsRegisterClass(MI, Value, 0, 0); |
| 1050 | break; |
| 1051 | } |
| 1052 | |
| 1053 | // op: g16_2 |
| 1054 | case Hexagon::S2_storeriabs: |
| 1055 | ++shift; |
| 1056 | // op: g16_1 |
| 1057 | case Hexagon::S2_storerhabs: |
| 1058 | case Hexagon::S2_storerfabs: |
| 1059 | ++shift; |
| 1060 | // op: g16_0 |
| 1061 | case Hexagon::S2_storerbabs: { |
| 1062 | Value = (insn >> 11) & UINT64_C(49152); |
| 1063 | Value |= (insn >> 7) & UINT64_C(15872); |
| 1064 | Value |= (insn >> 5) & UINT64_C(256); |
| 1065 | Value |= insn & UINT64_C(255); |
| 1066 | MI.addOperand(MCOperand::createImm(Value << shift)); |
| 1067 | // op: Rt |
| 1068 | Value = (insn >> 8) & UINT64_C(31); |
| 1069 | DecodeIntRegsRegisterClass(MI, Value, 0, 0); |
| 1070 | break; |
| 1071 | } |
| 1072 | } |
| 1073 | return MCDisassembler::Success; |
| 1074 | } |
| 1075 | return MCDisassembler::Fail; |
| 1076 | } |
| 1077 | |
| 1078 | static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, |
| 1079 | void const *Decoder) { |
| 1080 | |
| 1081 | // Instruction Class for a constant a extender: bits 31:28 = 0x0000 |
| 1082 | if ((~insn & 0xf0000000) == 0xf0000000) { |
| 1083 | unsigned Value; |
| 1084 | // 27:16 High 12 bits of 26-bit extender. |
| 1085 | Value = (insn & 0x0fff0000) << 4; |
| 1086 | // 13:0 Low 14 bits of 26-bit extender. |
| 1087 | Value |= ((insn & 0x3fff) << 6); |
| 1088 | MI.setOpcode(Hexagon::A4_ext); |
| 1089 | HexagonMCInstrInfo::addConstant(MI, Value, contextFromDecoder(Decoder)); |
| 1090 | return MCDisassembler::Success; |
| 1091 | } |
| 1092 | return MCDisassembler::Fail; |
| 1093 | } |
| 1094 | |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1095 | // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td |
| 1096 | enum subInstBinaryValues { |
| 1097 | V4_SA1_addi_BITS = 0x0000, |
| 1098 | V4_SA1_addi_MASK = 0x1800, |
| 1099 | V4_SA1_addrx_BITS = 0x1800, |
| 1100 | V4_SA1_addrx_MASK = 0x1f00, |
| 1101 | V4_SA1_addsp_BITS = 0x0c00, |
| 1102 | V4_SA1_addsp_MASK = 0x1c00, |
| 1103 | V4_SA1_and1_BITS = 0x1200, |
| 1104 | V4_SA1_and1_MASK = 0x1f00, |
| 1105 | V4_SA1_clrf_BITS = 0x1a70, |
| 1106 | V4_SA1_clrf_MASK = 0x1e70, |
| 1107 | V4_SA1_clrfnew_BITS = 0x1a50, |
| 1108 | V4_SA1_clrfnew_MASK = 0x1e70, |
| 1109 | V4_SA1_clrt_BITS = 0x1a60, |
| 1110 | V4_SA1_clrt_MASK = 0x1e70, |
| 1111 | V4_SA1_clrtnew_BITS = 0x1a40, |
| 1112 | V4_SA1_clrtnew_MASK = 0x1e70, |
| 1113 | V4_SA1_cmpeqi_BITS = 0x1900, |
| 1114 | V4_SA1_cmpeqi_MASK = 0x1f00, |
| 1115 | V4_SA1_combine0i_BITS = 0x1c00, |
| 1116 | V4_SA1_combine0i_MASK = 0x1d18, |
| 1117 | V4_SA1_combine1i_BITS = 0x1c08, |
| 1118 | V4_SA1_combine1i_MASK = 0x1d18, |
| 1119 | V4_SA1_combine2i_BITS = 0x1c10, |
| 1120 | V4_SA1_combine2i_MASK = 0x1d18, |
| 1121 | V4_SA1_combine3i_BITS = 0x1c18, |
| 1122 | V4_SA1_combine3i_MASK = 0x1d18, |
| 1123 | V4_SA1_combinerz_BITS = 0x1d08, |
| 1124 | V4_SA1_combinerz_MASK = 0x1d08, |
| 1125 | V4_SA1_combinezr_BITS = 0x1d00, |
| 1126 | V4_SA1_combinezr_MASK = 0x1d08, |
| 1127 | V4_SA1_dec_BITS = 0x1300, |
| 1128 | V4_SA1_dec_MASK = 0x1f00, |
| 1129 | V4_SA1_inc_BITS = 0x1100, |
| 1130 | V4_SA1_inc_MASK = 0x1f00, |
| 1131 | V4_SA1_seti_BITS = 0x0800, |
| 1132 | V4_SA1_seti_MASK = 0x1c00, |
| 1133 | V4_SA1_setin1_BITS = 0x1a00, |
| 1134 | V4_SA1_setin1_MASK = 0x1e40, |
| 1135 | V4_SA1_sxtb_BITS = 0x1500, |
| 1136 | V4_SA1_sxtb_MASK = 0x1f00, |
| 1137 | V4_SA1_sxth_BITS = 0x1400, |
| 1138 | V4_SA1_sxth_MASK = 0x1f00, |
| 1139 | V4_SA1_tfr_BITS = 0x1000, |
| 1140 | V4_SA1_tfr_MASK = 0x1f00, |
| 1141 | V4_SA1_zxtb_BITS = 0x1700, |
| 1142 | V4_SA1_zxtb_MASK = 0x1f00, |
| 1143 | V4_SA1_zxth_BITS = 0x1600, |
| 1144 | V4_SA1_zxth_MASK = 0x1f00, |
| 1145 | V4_SL1_loadri_io_BITS = 0x0000, |
| 1146 | V4_SL1_loadri_io_MASK = 0x1000, |
| 1147 | V4_SL1_loadrub_io_BITS = 0x1000, |
| 1148 | V4_SL1_loadrub_io_MASK = 0x1000, |
| 1149 | V4_SL2_deallocframe_BITS = 0x1f00, |
| 1150 | V4_SL2_deallocframe_MASK = 0x1fc0, |
| 1151 | V4_SL2_jumpr31_BITS = 0x1fc0, |
| 1152 | V4_SL2_jumpr31_MASK = 0x1fc4, |
| 1153 | V4_SL2_jumpr31_f_BITS = 0x1fc5, |
| 1154 | V4_SL2_jumpr31_f_MASK = 0x1fc7, |
| 1155 | V4_SL2_jumpr31_fnew_BITS = 0x1fc7, |
| 1156 | V4_SL2_jumpr31_fnew_MASK = 0x1fc7, |
| 1157 | V4_SL2_jumpr31_t_BITS = 0x1fc4, |
| 1158 | V4_SL2_jumpr31_t_MASK = 0x1fc7, |
| 1159 | V4_SL2_jumpr31_tnew_BITS = 0x1fc6, |
| 1160 | V4_SL2_jumpr31_tnew_MASK = 0x1fc7, |
| 1161 | V4_SL2_loadrb_io_BITS = 0x1000, |
| 1162 | V4_SL2_loadrb_io_MASK = 0x1800, |
| 1163 | V4_SL2_loadrd_sp_BITS = 0x1e00, |
| 1164 | V4_SL2_loadrd_sp_MASK = 0x1f00, |
| 1165 | V4_SL2_loadrh_io_BITS = 0x0000, |
| 1166 | V4_SL2_loadrh_io_MASK = 0x1800, |
| 1167 | V4_SL2_loadri_sp_BITS = 0x1c00, |
| 1168 | V4_SL2_loadri_sp_MASK = 0x1e00, |
| 1169 | V4_SL2_loadruh_io_BITS = 0x0800, |
| 1170 | V4_SL2_loadruh_io_MASK = 0x1800, |
| 1171 | V4_SL2_return_BITS = 0x1f40, |
| 1172 | V4_SL2_return_MASK = 0x1fc4, |
| 1173 | V4_SL2_return_f_BITS = 0x1f45, |
| 1174 | V4_SL2_return_f_MASK = 0x1fc7, |
| 1175 | V4_SL2_return_fnew_BITS = 0x1f47, |
| 1176 | V4_SL2_return_fnew_MASK = 0x1fc7, |
| 1177 | V4_SL2_return_t_BITS = 0x1f44, |
| 1178 | V4_SL2_return_t_MASK = 0x1fc7, |
| 1179 | V4_SL2_return_tnew_BITS = 0x1f46, |
| 1180 | V4_SL2_return_tnew_MASK = 0x1fc7, |
| 1181 | V4_SS1_storeb_io_BITS = 0x1000, |
| 1182 | V4_SS1_storeb_io_MASK = 0x1000, |
| 1183 | V4_SS1_storew_io_BITS = 0x0000, |
| 1184 | V4_SS1_storew_io_MASK = 0x1000, |
| 1185 | V4_SS2_allocframe_BITS = 0x1c00, |
| 1186 | V4_SS2_allocframe_MASK = 0x1e00, |
| 1187 | V4_SS2_storebi0_BITS = 0x1200, |
| 1188 | V4_SS2_storebi0_MASK = 0x1f00, |
| 1189 | V4_SS2_storebi1_BITS = 0x1300, |
| 1190 | V4_SS2_storebi1_MASK = 0x1f00, |
| 1191 | V4_SS2_stored_sp_BITS = 0x0a00, |
| 1192 | V4_SS2_stored_sp_MASK = 0x1e00, |
| 1193 | V4_SS2_storeh_io_BITS = 0x0000, |
| 1194 | V4_SS2_storeh_io_MASK = 0x1800, |
| 1195 | V4_SS2_storew_sp_BITS = 0x0800, |
| 1196 | V4_SS2_storew_sp_MASK = 0x1e00, |
| 1197 | V4_SS2_storewi0_BITS = 0x1000, |
| 1198 | V4_SS2_storewi0_MASK = 0x1f00, |
| 1199 | V4_SS2_storewi1_BITS = 0x1100, |
| 1200 | V4_SS2_storewi1_MASK = 0x1f00 |
| 1201 | }; |
| 1202 | |
| 1203 | static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, |
| 1204 | raw_ostream &os) { |
| 1205 | switch (IClass) { |
| 1206 | case HexagonII::HSIG_L1: |
| 1207 | if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS) |
| 1208 | op = Hexagon::V4_SL1_loadri_io; |
| 1209 | else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS) |
| 1210 | op = Hexagon::V4_SL1_loadrub_io; |
| 1211 | else { |
| 1212 | os << "<unknown subinstruction>"; |
| 1213 | return MCDisassembler::Fail; |
| 1214 | } |
| 1215 | break; |
| 1216 | case HexagonII::HSIG_L2: |
| 1217 | if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS) |
| 1218 | op = Hexagon::V4_SL2_deallocframe; |
| 1219 | else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS) |
| 1220 | op = Hexagon::V4_SL2_jumpr31; |
| 1221 | else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS) |
| 1222 | op = Hexagon::V4_SL2_jumpr31_f; |
| 1223 | else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS) |
| 1224 | op = Hexagon::V4_SL2_jumpr31_fnew; |
| 1225 | else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS) |
| 1226 | op = Hexagon::V4_SL2_jumpr31_t; |
| 1227 | else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS) |
| 1228 | op = Hexagon::V4_SL2_jumpr31_tnew; |
| 1229 | else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS) |
| 1230 | op = Hexagon::V4_SL2_loadrb_io; |
| 1231 | else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS) |
| 1232 | op = Hexagon::V4_SL2_loadrd_sp; |
| 1233 | else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS) |
| 1234 | op = Hexagon::V4_SL2_loadrh_io; |
| 1235 | else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS) |
| 1236 | op = Hexagon::V4_SL2_loadri_sp; |
| 1237 | else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS) |
| 1238 | op = Hexagon::V4_SL2_loadruh_io; |
| 1239 | else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS) |
| 1240 | op = Hexagon::V4_SL2_return; |
| 1241 | else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS) |
| 1242 | op = Hexagon::V4_SL2_return_f; |
| 1243 | else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS) |
| 1244 | op = Hexagon::V4_SL2_return_fnew; |
| 1245 | else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS) |
| 1246 | op = Hexagon::V4_SL2_return_t; |
| 1247 | else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS) |
| 1248 | op = Hexagon::V4_SL2_return_tnew; |
| 1249 | else { |
| 1250 | os << "<unknown subinstruction>"; |
| 1251 | return MCDisassembler::Fail; |
| 1252 | } |
| 1253 | break; |
| 1254 | case HexagonII::HSIG_A: |
| 1255 | if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS) |
| 1256 | op = Hexagon::V4_SA1_addi; |
| 1257 | else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS) |
| 1258 | op = Hexagon::V4_SA1_addrx; |
| 1259 | else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS) |
| 1260 | op = Hexagon::V4_SA1_addsp; |
| 1261 | else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS) |
| 1262 | op = Hexagon::V4_SA1_and1; |
| 1263 | else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS) |
| 1264 | op = Hexagon::V4_SA1_clrf; |
| 1265 | else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS) |
| 1266 | op = Hexagon::V4_SA1_clrfnew; |
| 1267 | else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS) |
| 1268 | op = Hexagon::V4_SA1_clrt; |
| 1269 | else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS) |
| 1270 | op = Hexagon::V4_SA1_clrtnew; |
| 1271 | else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS) |
| 1272 | op = Hexagon::V4_SA1_cmpeqi; |
| 1273 | else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS) |
| 1274 | op = Hexagon::V4_SA1_combine0i; |
| 1275 | else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS) |
| 1276 | op = Hexagon::V4_SA1_combine1i; |
| 1277 | else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS) |
| 1278 | op = Hexagon::V4_SA1_combine2i; |
| 1279 | else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS) |
| 1280 | op = Hexagon::V4_SA1_combine3i; |
| 1281 | else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS) |
| 1282 | op = Hexagon::V4_SA1_combinerz; |
| 1283 | else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS) |
| 1284 | op = Hexagon::V4_SA1_combinezr; |
| 1285 | else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS) |
| 1286 | op = Hexagon::V4_SA1_dec; |
| 1287 | else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS) |
| 1288 | op = Hexagon::V4_SA1_inc; |
| 1289 | else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS) |
| 1290 | op = Hexagon::V4_SA1_seti; |
| 1291 | else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS) |
| 1292 | op = Hexagon::V4_SA1_setin1; |
| 1293 | else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS) |
| 1294 | op = Hexagon::V4_SA1_sxtb; |
| 1295 | else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS) |
| 1296 | op = Hexagon::V4_SA1_sxth; |
| 1297 | else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS) |
| 1298 | op = Hexagon::V4_SA1_tfr; |
| 1299 | else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS) |
| 1300 | op = Hexagon::V4_SA1_zxtb; |
| 1301 | else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS) |
| 1302 | op = Hexagon::V4_SA1_zxth; |
| 1303 | else { |
| 1304 | os << "<unknown subinstruction>"; |
| 1305 | return MCDisassembler::Fail; |
| 1306 | } |
| 1307 | break; |
| 1308 | case HexagonII::HSIG_S1: |
| 1309 | if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS) |
| 1310 | op = Hexagon::V4_SS1_storeb_io; |
| 1311 | else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS) |
| 1312 | op = Hexagon::V4_SS1_storew_io; |
| 1313 | else { |
| 1314 | os << "<unknown subinstruction>"; |
| 1315 | return MCDisassembler::Fail; |
| 1316 | } |
| 1317 | break; |
| 1318 | case HexagonII::HSIG_S2: |
| 1319 | if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS) |
| 1320 | op = Hexagon::V4_SS2_allocframe; |
| 1321 | else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS) |
| 1322 | op = Hexagon::V4_SS2_storebi0; |
| 1323 | else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS) |
| 1324 | op = Hexagon::V4_SS2_storebi1; |
| 1325 | else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS) |
| 1326 | op = Hexagon::V4_SS2_stored_sp; |
| 1327 | else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS) |
| 1328 | op = Hexagon::V4_SS2_storeh_io; |
| 1329 | else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS) |
| 1330 | op = Hexagon::V4_SS2_storew_sp; |
| 1331 | else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS) |
| 1332 | op = Hexagon::V4_SS2_storewi0; |
| 1333 | else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS) |
| 1334 | op = Hexagon::V4_SS2_storewi1; |
| 1335 | else { |
| 1336 | os << "<unknown subinstruction>"; |
| 1337 | return MCDisassembler::Fail; |
| 1338 | } |
| 1339 | break; |
| 1340 | default: |
| 1341 | os << "<unknown>"; |
| 1342 | return MCDisassembler::Fail; |
| 1343 | } |
| 1344 | return MCDisassembler::Success; |
| 1345 | } |
| 1346 | |
| 1347 | static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) { |
| 1348 | if (encoded_reg < 8) |
| 1349 | return Hexagon::R0 + encoded_reg; |
| 1350 | else if (encoded_reg < 16) |
| 1351 | return Hexagon::R0 + encoded_reg + 8; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1352 | |
| 1353 | // patently false value |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1354 | return Hexagon::NoRegister; |
| 1355 | } |
| 1356 | |
| 1357 | static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) { |
| 1358 | if (encoded_dreg < 4) |
| 1359 | return Hexagon::D0 + encoded_dreg; |
| 1360 | else if (encoded_dreg < 8) |
| 1361 | return Hexagon::D0 + encoded_dreg + 4; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1362 | |
| 1363 | // patently false value |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1364 | return Hexagon::NoRegister; |
| 1365 | } |
| 1366 | |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1367 | void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode, |
| 1368 | unsigned inst) const { |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1369 | int64_t operand; |
| 1370 | MCOperand Op; |
| 1371 | switch (opcode) { |
| 1372 | case Hexagon::V4_SL2_deallocframe: |
| 1373 | case Hexagon::V4_SL2_jumpr31: |
| 1374 | case Hexagon::V4_SL2_jumpr31_f: |
| 1375 | case Hexagon::V4_SL2_jumpr31_fnew: |
| 1376 | case Hexagon::V4_SL2_jumpr31_t: |
| 1377 | case Hexagon::V4_SL2_jumpr31_tnew: |
| 1378 | case Hexagon::V4_SL2_return: |
| 1379 | case Hexagon::V4_SL2_return_f: |
| 1380 | case Hexagon::V4_SL2_return_fnew: |
| 1381 | case Hexagon::V4_SL2_return_t: |
| 1382 | case Hexagon::V4_SL2_return_tnew: |
| 1383 | // no operands for these instructions |
| 1384 | break; |
| 1385 | case Hexagon::V4_SS2_allocframe: |
| 1386 | // u 8-4{5_3} |
| 1387 | operand = ((inst & 0x1f0) >> 4) << 3; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1388 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1389 | break; |
| 1390 | case Hexagon::V4_SL1_loadri_io: |
| 1391 | // Rd 3-0, Rs 7-4, u 11-8{4_2} |
| 1392 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1393 | Op = MCOperand::createReg(operand); |
| 1394 | MI->addOperand(Op); |
| 1395 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1396 | Op = MCOperand::createReg(operand); |
| 1397 | MI->addOperand(Op); |
| 1398 | operand = (inst & 0xf00) >> 6; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1399 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1400 | break; |
| 1401 | case Hexagon::V4_SL1_loadrub_io: |
| 1402 | // Rd 3-0, Rs 7-4, u 11-8 |
| 1403 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1404 | Op = MCOperand::createReg(operand); |
| 1405 | MI->addOperand(Op); |
| 1406 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1407 | Op = MCOperand::createReg(operand); |
| 1408 | MI->addOperand(Op); |
| 1409 | operand = (inst & 0xf00) >> 8; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1410 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1411 | break; |
| 1412 | case Hexagon::V4_SL2_loadrb_io: |
| 1413 | // Rd 3-0, Rs 7-4, u 10-8 |
| 1414 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1415 | Op = MCOperand::createReg(operand); |
| 1416 | MI->addOperand(Op); |
| 1417 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1418 | Op = MCOperand::createReg(operand); |
| 1419 | MI->addOperand(Op); |
| 1420 | operand = (inst & 0x700) >> 8; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1421 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1422 | break; |
| 1423 | case Hexagon::V4_SL2_loadrh_io: |
| 1424 | case Hexagon::V4_SL2_loadruh_io: |
| 1425 | // Rd 3-0, Rs 7-4, u 10-8{3_1} |
| 1426 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1427 | Op = MCOperand::createReg(operand); |
| 1428 | MI->addOperand(Op); |
| 1429 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1430 | Op = MCOperand::createReg(operand); |
| 1431 | MI->addOperand(Op); |
| 1432 | operand = ((inst & 0x700) >> 8) << 1; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1433 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1434 | break; |
| 1435 | case Hexagon::V4_SL2_loadrd_sp: |
| 1436 | // Rdd 2-0, u 7-3{5_3} |
| 1437 | operand = getDRegFromSubinstEncoding(inst & 0x7); |
| 1438 | Op = MCOperand::createReg(operand); |
| 1439 | MI->addOperand(Op); |
| 1440 | operand = ((inst & 0x0f8) >> 3) << 3; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1441 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1442 | break; |
| 1443 | case Hexagon::V4_SL2_loadri_sp: |
| 1444 | // Rd 3-0, u 8-4{5_2} |
| 1445 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1446 | Op = MCOperand::createReg(operand); |
| 1447 | MI->addOperand(Op); |
| 1448 | operand = ((inst & 0x1f0) >> 4) << 2; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1449 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1450 | break; |
| 1451 | case Hexagon::V4_SA1_addi: |
| 1452 | // Rx 3-0 (x2), s7 10-4 |
| 1453 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1454 | Op = MCOperand::createReg(operand); |
| 1455 | MI->addOperand(Op); |
| 1456 | MI->addOperand(Op); |
| 1457 | operand = SignExtend64<7>((inst & 0x7f0) >> 4); |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1458 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1459 | break; |
| 1460 | case Hexagon::V4_SA1_addrx: |
| 1461 | // Rx 3-0 (x2), Rs 7-4 |
| 1462 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1463 | Op = MCOperand::createReg(operand); |
| 1464 | MI->addOperand(Op); |
| 1465 | MI->addOperand(Op); |
| 1466 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1467 | Op = MCOperand::createReg(operand); |
| 1468 | MI->addOperand(Op); |
| 1469 | case Hexagon::V4_SA1_and1: |
| 1470 | case Hexagon::V4_SA1_dec: |
| 1471 | case Hexagon::V4_SA1_inc: |
| 1472 | case Hexagon::V4_SA1_sxtb: |
| 1473 | case Hexagon::V4_SA1_sxth: |
| 1474 | case Hexagon::V4_SA1_tfr: |
| 1475 | case Hexagon::V4_SA1_zxtb: |
| 1476 | case Hexagon::V4_SA1_zxth: |
| 1477 | // Rd 3-0, Rs 7-4 |
| 1478 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1479 | Op = MCOperand::createReg(operand); |
| 1480 | MI->addOperand(Op); |
| 1481 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1482 | Op = MCOperand::createReg(operand); |
| 1483 | MI->addOperand(Op); |
| 1484 | break; |
| 1485 | case Hexagon::V4_SA1_addsp: |
| 1486 | // Rd 3-0, u 9-4{6_2} |
| 1487 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1488 | Op = MCOperand::createReg(operand); |
| 1489 | MI->addOperand(Op); |
| 1490 | operand = ((inst & 0x3f0) >> 4) << 2; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1491 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1492 | break; |
| 1493 | case Hexagon::V4_SA1_seti: |
| 1494 | // Rd 3-0, u 9-4 |
| 1495 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1496 | Op = MCOperand::createReg(operand); |
| 1497 | MI->addOperand(Op); |
| 1498 | operand = (inst & 0x3f0) >> 4; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1499 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1500 | break; |
| 1501 | case Hexagon::V4_SA1_clrf: |
| 1502 | case Hexagon::V4_SA1_clrfnew: |
| 1503 | case Hexagon::V4_SA1_clrt: |
| 1504 | case Hexagon::V4_SA1_clrtnew: |
| 1505 | case Hexagon::V4_SA1_setin1: |
| 1506 | // Rd 3-0 |
| 1507 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1508 | Op = MCOperand::createReg(operand); |
| 1509 | MI->addOperand(Op); |
| 1510 | break; |
| 1511 | case Hexagon::V4_SA1_cmpeqi: |
| 1512 | // Rs 7-4, u 1-0 |
| 1513 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1514 | Op = MCOperand::createReg(operand); |
| 1515 | MI->addOperand(Op); |
| 1516 | operand = inst & 0x3; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1517 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1518 | break; |
| 1519 | case Hexagon::V4_SA1_combine0i: |
| 1520 | case Hexagon::V4_SA1_combine1i: |
| 1521 | case Hexagon::V4_SA1_combine2i: |
| 1522 | case Hexagon::V4_SA1_combine3i: |
| 1523 | // Rdd 2-0, u 6-5 |
| 1524 | operand = getDRegFromSubinstEncoding(inst & 0x7); |
| 1525 | Op = MCOperand::createReg(operand); |
| 1526 | MI->addOperand(Op); |
| 1527 | operand = (inst & 0x060) >> 5; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1528 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1529 | break; |
| 1530 | case Hexagon::V4_SA1_combinerz: |
| 1531 | case Hexagon::V4_SA1_combinezr: |
| 1532 | // Rdd 2-0, Rs 7-4 |
| 1533 | operand = getDRegFromSubinstEncoding(inst & 0x7); |
| 1534 | Op = MCOperand::createReg(operand); |
| 1535 | MI->addOperand(Op); |
| 1536 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1537 | Op = MCOperand::createReg(operand); |
| 1538 | MI->addOperand(Op); |
| 1539 | break; |
| 1540 | case Hexagon::V4_SS1_storeb_io: |
| 1541 | // Rs 7-4, u 11-8, Rt 3-0 |
| 1542 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1543 | Op = MCOperand::createReg(operand); |
| 1544 | MI->addOperand(Op); |
| 1545 | operand = (inst & 0xf00) >> 8; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1546 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1547 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1548 | Op = MCOperand::createReg(operand); |
| 1549 | MI->addOperand(Op); |
| 1550 | break; |
| 1551 | case Hexagon::V4_SS1_storew_io: |
| 1552 | // Rs 7-4, u 11-8{4_2}, Rt 3-0 |
| 1553 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1554 | Op = MCOperand::createReg(operand); |
| 1555 | MI->addOperand(Op); |
| 1556 | operand = ((inst & 0xf00) >> 8) << 2; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1557 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1558 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1559 | Op = MCOperand::createReg(operand); |
| 1560 | MI->addOperand(Op); |
| 1561 | break; |
| 1562 | case Hexagon::V4_SS2_storebi0: |
| 1563 | case Hexagon::V4_SS2_storebi1: |
| 1564 | // Rs 7-4, u 3-0 |
| 1565 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1566 | Op = MCOperand::createReg(operand); |
| 1567 | MI->addOperand(Op); |
| 1568 | operand = inst & 0xf; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1569 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1570 | break; |
| 1571 | case Hexagon::V4_SS2_storewi0: |
| 1572 | case Hexagon::V4_SS2_storewi1: |
| 1573 | // Rs 7-4, u 3-0{4_2} |
| 1574 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1575 | Op = MCOperand::createReg(operand); |
| 1576 | MI->addOperand(Op); |
| 1577 | operand = (inst & 0xf) << 2; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1578 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1579 | break; |
| 1580 | case Hexagon::V4_SS2_stored_sp: |
| 1581 | // s 8-3{6_3}, Rtt 2-0 |
| 1582 | operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3); |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1583 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1584 | operand = getDRegFromSubinstEncoding(inst & 0x7); |
| 1585 | Op = MCOperand::createReg(operand); |
| 1586 | MI->addOperand(Op); |
Colin LeMahieu | 160f73e | 2015-11-03 00:21:19 +0000 | [diff] [blame] | 1587 | break; |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1588 | case Hexagon::V4_SS2_storeh_io: |
| 1589 | // Rs 7-4, u 10-8{3_1}, Rt 3-0 |
| 1590 | operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); |
| 1591 | Op = MCOperand::createReg(operand); |
| 1592 | MI->addOperand(Op); |
| 1593 | operand = ((inst & 0x700) >> 8) << 1; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1594 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1595 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1596 | Op = MCOperand::createReg(operand); |
| 1597 | MI->addOperand(Op); |
| 1598 | break; |
| 1599 | case Hexagon::V4_SS2_storew_sp: |
| 1600 | // u 8-4{5_2}, Rd 3-0 |
| 1601 | operand = ((inst & 0x1f0) >> 4) << 2; |
Colin LeMahieu | 7cd0892 | 2015-11-09 04:07:48 +0000 | [diff] [blame] | 1602 | HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 1603 | operand = getRegFromSubinstEncoding(inst & 0xf); |
| 1604 | Op = MCOperand::createReg(operand); |
| 1605 | MI->addOperand(Op); |
| 1606 | break; |
| 1607 | default: |
| 1608 | // don't crash with an invalid subinstruction |
| 1609 | // llvm_unreachable("Invalid subinstruction in duplex instruction"); |
| 1610 | break; |
| 1611 | } |
| 1612 | } |