| Vincent Lejeune | 1ce13f5 | 2013-02-18 14:11:28 +0000 | [diff] [blame] | 1 | ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s |
| 2 | |
| Vincent Lejeune | 4b5b849 | 2013-06-05 20:27:35 +0000 | [diff] [blame] | 3 | ;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} |
| Vincent Lejeune | 1ce13f5 | 2013-02-18 14:11:28 +0000 | [diff] [blame] | 4 | |
| Nicolai Haehnle | df3a20c | 2016-04-06 19:40:20 +0000 | [diff] [blame] | 5 | define amdgpu_ps void @test(<4 x float> inreg %reg0) { |
| Vincent Lejeune | f143af3 | 2013-11-11 22:10:24 +0000 | [diff] [blame] | 6 | %r0 = extractelement <4 x float> %reg0, i32 0 |
| 7 | %r1 = extractelement <4 x float> %reg0, i32 1 |
| 8 | %r2 = extractelement <4 x float> %reg0, i32 2 |
| Vincent Lejeune | 1ce13f5 | 2013-02-18 14:11:28 +0000 | [diff] [blame] | 9 | %r3 = fmul float %r0, %r1 |
| Vincent Lejeune | f143af3 | 2013-11-11 22:10:24 +0000 | [diff] [blame] | 10 | %r4 = fadd float %r3, %r2 |
| 11 | %vec = insertelement <4 x float> undef, float %r4, i32 0 |
| Matt Arsenault | 82e5e1e | 2016-07-15 21:27:08 +0000 | [diff] [blame] | 12 | call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) |
| Vincent Lejeune | 1ce13f5 | 2013-02-18 14:11:28 +0000 | [diff] [blame] | 13 | ret void |
| 14 | } |
| 15 | |
| Vincent Lejeune | 1ce13f5 | 2013-02-18 14:11:28 +0000 | [diff] [blame] | 16 | declare float @fabs(float ) readnone |
| Matt Arsenault | 82e5e1e | 2016-07-15 21:27:08 +0000 | [diff] [blame] | 17 | declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) |