Vincent Lejeune | 745d429 | 2013-11-16 16:24:41 +0000 | [diff] [blame] | 1 | ;RUN: llc < %s -march=r600 -mcpu=cayman |
| 2 | |
Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 3 | ; CHECK-LABEL: {{^}}main: |
Vincent Lejeune | 745d429 | 2013-11-16 16:24:41 +0000 | [diff] [blame] | 4 | ; CHECK: PRED_SETE_INT * Pred, |
| 5 | ; CHECK: DOT4 T{{[0-9]+}}.X, T0.X, T0.X, Pred_sel_one |
Nicolai Haehnle | df3a20c | 2016-04-06 19:40:20 +0000 | [diff] [blame] | 6 | define amdgpu_ps void @main(<4 x float> inreg) { |
Vincent Lejeune | 745d429 | 2013-11-16 16:24:41 +0000 | [diff] [blame] | 7 | main_body: |
| 8 | %1 = extractelement <4 x float> %0, i32 0 |
| 9 | %2 = bitcast float %1 to i32 |
| 10 | %3 = icmp eq i32 %2, 0 |
| 11 | br i1 %3, label %IF, label %ENDIF |
| 12 | |
| 13 | IF: ; preds = %main_body |
Matt Arsenault | ca7f570 | 2016-07-14 05:47:17 +0000 | [diff] [blame] | 14 | %4 = call float @llvm.r600.dot4(<4 x float> %0, <4 x float> %0) |
Vincent Lejeune | 745d429 | 2013-11-16 16:24:41 +0000 | [diff] [blame] | 15 | br label %ENDIF |
| 16 | |
| 17 | ENDIF: ; preds = %IF, %main_body |
| 18 | %5 = phi float [%4, %IF], [0.000000e+00, %main_body] |
| 19 | %6 = insertelement <4 x float> undef, float %5, i32 0 |
Matt Arsenault | 82e5e1e | 2016-07-15 21:27:08 +0000 | [diff] [blame] | 20 | call void @llvm.r600.store.swizzle(<4 x float> %6, i32 0, i32 0) |
Vincent Lejeune | 745d429 | 2013-11-16 16:24:41 +0000 | [diff] [blame] | 21 | ret void |
| 22 | } |
| 23 | |
Matt Arsenault | ca7f570 | 2016-07-14 05:47:17 +0000 | [diff] [blame] | 24 | declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1 |
Matt Arsenault | 82e5e1e | 2016-07-15 21:27:08 +0000 | [diff] [blame] | 25 | declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) |
Vincent Lejeune | 745d429 | 2013-11-16 16:24:41 +0000 | [diff] [blame] | 26 | attributes #1 = { readnone } |