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gerrit-public.fairphone.software / toolchain / llvm-project / 00b51bf123d83d19b4dfc916676a7aed1b9da41e / . / llvm / test / CodeGen / AMDGPU / select64.ll
blob: 3b4c925a87a090e40290b8f4b05596c78dd5479b [file] [log] [blame]
Tom Stellard49f8bfd2015-01-06 18:00:21 +0000[diff] [blame]1; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
Marek Olsak75170772015-01-27 17:27:15 +0000[diff] [blame]2; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
Tom Stellard0ec134f2014-02-04 17:18:40 +0000[diff] [blame]3
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]4; CHECK-LABEL: {{^}}select0:
Tom Stellard7ea3d6d2014-03-31 14:01:55 +0000[diff] [blame]5; i64 select should be split into two i32 selects, and we shouldn't need
6; to use a shfit to extract the hi dword of the input.
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]7; CHECK-NOT: s_lshr_b64
8; CHECK: v_cndmask
9; CHECK: v_cndmask
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]10define amdgpu_kernel void @select0(i64 addrspace(1)* %out, i32 %cond, i64 %in) {
Tom Stellard0ec134f2014-02-04 17:18:40 +0000[diff] [blame]11entry:
12 %0 = icmp ugt i32 %cond, 5
13 %1 = select i1 %0, i64 0, i64 %in
14 store i64 %1, i64 addrspace(1)* %out
15 ret void
16}
Matt Arsenault3332b702014-07-10 18:21:04 +0000[diff] [blame]17
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]18; CHECK-LABEL: {{^}}select_trunc_i64:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]19; CHECK: v_cndmask_b32
20; CHECK-NOT: v_cndmask_b32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]21define amdgpu_kernel void @select_trunc_i64(i32 addrspace(1)* %out, i32 %cond, i64 %in) nounwind {
Matt Arsenault3332b702014-07-10 18:21:04 +0000[diff] [blame]22 %cmp = icmp ugt i32 %cond, 5
23 %sel = select i1 %cmp, i64 0, i64 %in
24 %trunc = trunc i64 %sel to i32
25 store i32 %trunc, i32 addrspace(1)* %out, align 4
26 ret void
27}
28
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]29; CHECK-LABEL: {{^}}select_trunc_i64_2:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]30; CHECK: v_cndmask_b32
31; CHECK-NOT: v_cndmask_b32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]32define amdgpu_kernel void @select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 %a, i64 %b) nounwind {
Matt Arsenault3332b702014-07-10 18:21:04 +0000[diff] [blame]33 %cmp = icmp ugt i32 %cond, 5
34 %sel = select i1 %cmp, i64 %a, i64 %b
35 %trunc = trunc i64 %sel to i32
36 store i32 %trunc, i32 addrspace(1)* %out, align 4
37 ret void
38}
39
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]40; CHECK-LABEL: {{^}}v_select_trunc_i64_2:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]41; CHECK: v_cndmask_b32
42; CHECK-NOT: v_cndmask_b32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]43define amdgpu_kernel void @v_select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
Matt Arsenault3332b702014-07-10 18:21:04 +0000[diff] [blame]44 %cmp = icmp ugt i32 %cond, 5
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]45 %a = load i64, i64 addrspace(1)* %aptr, align 8
46 %b = load i64, i64 addrspace(1)* %bptr, align 8
Matt Arsenault3332b702014-07-10 18:21:04 +0000[diff] [blame]47 %sel = select i1 %cmp, i64 %a, i64 %b
48 %trunc = trunc i64 %sel to i32
49 store i32 %trunc, i32 addrspace(1)* %out, align 4
50 ret void
51}
Matt Arsenault11a4d672015-02-13 19:05:03 +0000[diff] [blame]52
53; CHECK-LABEL: {{^}}v_select_i64_split_imm:
Tom Stellard9a197672015-09-09 15:43:26 +0000[diff] [blame]54; CHECK-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
55; CHECK-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 63, {{v[0-9]+}}
Matt Arsenault11a4d672015-02-13 19:05:03 +0000[diff] [blame]56; CHECK: s_endpgm
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]57define amdgpu_kernel void @v_select_i64_split_imm(i64 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
Matt Arsenault11a4d672015-02-13 19:05:03 +0000[diff] [blame]58 %cmp = icmp ugt i32 %cond, 5
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]59 %a = load i64, i64 addrspace(1)* %aptr, align 8
60 %b = load i64, i64 addrspace(1)* %bptr, align 8
Matt Arsenault11a4d672015-02-13 19:05:03 +0000[diff] [blame]61 %sel = select i1 %cmp, i64 %a, i64 270582939648 ; 63 << 32
62 store i64 %sel, i64 addrspace(1)* %out, align 8
63 ret void
64}