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gerrit-public.fairphone.software / toolchain / llvm-project / 012dd42e027e2ff3d183cc9dcf27004cf9711720 / . / llvm / lib / Support / X86TargetParser.cpp
blob: 35582a9b277cc691dd91684cdaa9722384ee02ab [file] [log] [blame]
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/Support/X86TargetParser.h"
14#include "llvm/ADT/StringSwitch.h"
15#include "llvm/ADT/Triple.h"
16
17using namespace llvm;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]18using namespace llvm::X86;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]19
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]20namespace {
21
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]22/// Container class for CPU features.
23/// This is a constexpr reimplementation of a subset of std::bitset. It would be
24/// nice to use std::bitset directly, but it doesn't support constant
25/// initialization.
26class FeatureBitset {
27 static constexpr unsigned NUM_FEATURE_WORDS =
28 (X86::CPU_FEATURE_MAX + 31) / 32;
29
30 // This cannot be a std::array, operator[] is not constexpr until C++17.
31 uint32_t Bits[NUM_FEATURE_WORDS] = {};
32
33public:
34 constexpr FeatureBitset() = default;
35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36 for (auto I : Init)
37 set(I);
38 }
39
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]40 bool any() const {
41 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
42 }
43
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]44 constexpr FeatureBitset &set(unsigned I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]45 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]46 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
47 Bits[I / 32] = NewBits;
48 return *this;
49 }
50
51 constexpr bool operator[](unsigned I) const {
52 uint32_t Mask = uint32_t(1) << (I % 32);
53 return (Bits[I / 32] & Mask) != 0;
54 }
55
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]56 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
57 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
58 // GCC <6.2 crashes if this is written in a single statement.
59 uint32_t NewBits = Bits[I] & RHS.Bits[I];
60 Bits[I] = NewBits;
61 }
62 return *this;
63 }
64
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]65 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
66 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]67 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]68 uint32_t NewBits = Bits[I] | RHS.Bits[I];
69 Bits[I] = NewBits;
70 }
71 return *this;
72 }
73
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]74 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]75 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]76 FeatureBitset Result;
77 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
78 Result.Bits[I] = Bits[I] & RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]79 return Result;
80 }
81
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]82 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]83 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]84 FeatureBitset Result;
85 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
86 Result.Bits[I] = Bits[I] | RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]87 return Result;
88 }
89
90 constexpr FeatureBitset operator~() const {
91 FeatureBitset Result;
92 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
93 Result.Bits[I] = ~Bits[I];
94 return Result;
95 }
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]96
97 constexpr bool operator!=(const FeatureBitset &RHS) const {
98 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
99 if (Bits[I] != RHS.Bits[I])
100 return true;
101 return false;
102 }
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]103};
104
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]105struct ProcInfo {
106 StringLiteral Name;
107 X86::CPUKind Kind;
108 unsigned KeyFeature;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]109 FeatureBitset Features;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]110};
111
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]112struct FeatureInfo {
113 StringLiteral Name;
114 FeatureBitset ImpliedFeatures;
115};
116
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]117} // end anonymous namespace
118
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]119#define X86_FEATURE(ENUM, STRING) \
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]120 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]121#include "llvm/Support/X86TargetParser.def"
122
123// Pentium with MMX.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]124constexpr FeatureBitset FeaturesPentiumMMX =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]125 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
126
127// Pentium 2 and 3.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]128constexpr FeatureBitset FeaturesPentium2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]129 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]130constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]131
132// Pentium 4 CPUs
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]133constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
134constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
135constexpr FeatureBitset FeaturesNocona =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]136 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]137
138// Basic 64-bit capable CPU.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]139constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame^]140constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
141 FeaturePOPCNT | FeatureSSE4_2 |
142 FeatureCMPXCHG16B;
143constexpr FeatureBitset FeaturesX86_64_V3 =
144 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
145 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
146constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 |
147 FeatureAVX512BW | FeatureAVX512CD |
148 FeatureAVX512DQ | FeatureAVX512VL;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]149
150// Intel Core CPUs
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]151constexpr FeatureBitset FeaturesCore2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]152 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]153constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
154constexpr FeatureBitset FeaturesNehalem =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]155 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]156constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
157constexpr FeatureBitset FeaturesSandyBridge =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]158 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]159constexpr FeatureBitset FeaturesIvyBridge =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]160 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]161constexpr FeatureBitset FeaturesHaswell =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]162 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
163 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]164constexpr FeatureBitset FeaturesBroadwell =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]165 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
166
167// Intel Knights Landing and Knights Mill
168// Knights Landing has feature parity with Broadwell.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]169constexpr FeatureBitset FeaturesKNL =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]170 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
171 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]172constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]173
174// Intel Skylake processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]175constexpr FeatureBitset FeaturesSkylakeClient =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]176 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
177 FeatureXSAVES | FeatureSGX;
178// SkylakeServer inherits all SkylakeClient features except SGX.
179// FIXME: That doesn't match gcc.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]180constexpr FeatureBitset FeaturesSkylakeServer =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]181 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
182 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
183 FeaturePKU;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]184constexpr FeatureBitset FeaturesCascadeLake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]185 FeaturesSkylakeServer | FeatureAVX512VNNI;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]186constexpr FeatureBitset FeaturesCooperLake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]187 FeaturesCascadeLake | FeatureAVX512BF16;
188
189// Intel 10nm processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]190constexpr FeatureBitset FeaturesCannonlake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]191 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
192 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
193 FeaturePKU | FeatureSHA;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]194constexpr FeatureBitset FeaturesICLClient =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]195 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
196 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
197 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]198constexpr FeatureBitset FeaturesICLServer =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]199 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]200constexpr FeatureBitset FeaturesTigerlake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]201 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]202 FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]203constexpr FeatureBitset FeaturesSapphireRapids =
Freddy Yee02d0812020-08-25 12:27:02 +0800[diff] [blame]204 FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]205 FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE |
206 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
207 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]208
209// Intel Atom processors.
210// Bonnell has feature parity with Core2 and adds MOVBE.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]211constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]212// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]213constexpr FeatureBitset FeaturesSilvermont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]214 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]215constexpr FeatureBitset FeaturesGoldmont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]216 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
217 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
218 FeatureXSAVEOPT | FeatureXSAVES;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]219constexpr FeatureBitset FeaturesGoldmontPlus =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]220 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]221constexpr FeatureBitset FeaturesTremont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]222 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
223
224// Geode Processor.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]225constexpr FeatureBitset FeaturesGeode =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]226 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
227
228// K6 processor.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]229constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]230
231// K7 and K8 architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]232constexpr FeatureBitset FeaturesAthlon =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]233 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]234constexpr FeatureBitset FeaturesAthlonXP =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]235 FeaturesAthlon | FeatureFXSR | FeatureSSE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]236constexpr FeatureBitset FeaturesK8 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]237 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]238constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
239constexpr FeatureBitset FeaturesAMDFAM10 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]240 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]241 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]242
243// Bobcat architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]244constexpr FeatureBitset FeaturesBTVER1 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]245 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]246 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]247 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]248 FeatureSAHF;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]249constexpr FeatureBitset FeaturesBTVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]250 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
251 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
252
253// AMD Bulldozer architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]254constexpr FeatureBitset FeaturesBDVER1 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]255 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]256 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]257 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
258 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]259 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]260constexpr FeatureBitset FeaturesBDVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]261 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]262constexpr FeatureBitset FeaturesBDVER3 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]263 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]264constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
265 FeatureBMI2 | FeatureMOVBE |
266 FeatureMWAITX | FeatureRDRND;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]267
268// AMD Zen architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]269constexpr FeatureBitset FeaturesZNVER1 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]270 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
271 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]272 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]273 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
274 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
275 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
276 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]277 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]278 FeatureXSAVEOPT | FeatureXSAVES;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]279constexpr FeatureBitset FeaturesZNVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]280 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]281
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]282constexpr ProcInfo Processors[] = {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]283 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
284 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]285 // i386-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]286 { {"i386"}, CK_i386, ~0U, FeatureX87 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]287 // i486-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]288 { {"i486"}, CK_i486, ~0U, FeatureX87 },
289 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
290 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
291 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]292 // i586-generation processors, P5 microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]293 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
294 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
295 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]296 // i686-generation processors, P6 / Pentium M microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]297 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
298 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
299 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
300 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
301 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
302 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
303 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
304 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]305 // Netburst microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]306 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
307 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
308 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
309 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]310 // Core microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]311 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
312 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]313 // Atom processors
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]314 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
315 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
316 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
317 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
318 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
319 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
320 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]321 // Nehalem microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]322 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
323 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]324 // Westmere microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]325 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]326 // Sandy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]327 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
328 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]329 // Ivy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]330 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
331 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]332 // Haswell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]333 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
334 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]335 // Broadwell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]336 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]337 // Skylake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]338 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]339 // Skylake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]340 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
341 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]342 // Cascadelake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]343 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]344 // Cooperlake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]345 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]346 // Cannonlake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]347 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]348 // Icelake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]349 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]350 // Icelake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]351 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]352 // Tigerlake microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]353 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
Freddy Yee02d0812020-08-25 12:27:02 +0800[diff] [blame]354 // Sapphire Rapids microarchitecture based processors.
355 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]356 // Knights Landing processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]357 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]358 // Knights Mill processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]359 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]360 // Lakemont microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]361 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]362 // K6 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]363 { {"k6"}, CK_K6, ~0U, FeaturesK6 },
364 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
365 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]366 // K7 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]367 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
368 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
369 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
370 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
371 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]372 // K8 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]373 { {"k8"}, CK_K8, ~0U, FeaturesK8 },
374 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
375 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
376 { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
377 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
378 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
379 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
380 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
381 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]382 // Bobcat architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]383 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
384 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]385 // Bulldozer architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]386 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
387 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
388 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
389 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]390 // Zen architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]391 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
392 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]393 // Generic 64-bit processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]394 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame^]395 { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
396 { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
397 { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]398 // Geode processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]399 { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]400};
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]401
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame^]402constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
403
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]404X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]405 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]406 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]407 return P.Kind;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]408
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]409 return CK_None;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]410}
411
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame^]412X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
413 if (llvm::is_contained(NoTuneList, CPU))
414 return CK_None;
415 return parseArchX86(CPU, Only64Bit);
416}
417
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]418void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
419 bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]420 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]421 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]422 Values.emplace_back(P.Name);
423}
424
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame^]425void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
426 bool Only64Bit) {
427 for (const ProcInfo &P : Processors)
428 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
429 !llvm::is_contained(NoTuneList, P.Name))
430 Values.emplace_back(P.Name);
431}
432
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]433ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
434 // FIXME: Can we avoid a linear search here? The table might be sorted by
435 // CPUKind so we could binary search?
436 for (const auto &P : Processors) {
437 if (P.Kind == Kind) {
438 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
439 return static_cast<ProcessorFeatures>(P.KeyFeature);
440 }
441 }
442
443 llvm_unreachable("Unable to find CPU kind!");
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]444}
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]445
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]446// Features with no dependencies.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]447constexpr FeatureBitset ImpliedFeatures64BIT = {};
448constexpr FeatureBitset ImpliedFeaturesADX = {};
449constexpr FeatureBitset ImpliedFeaturesBMI = {};
450constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
451constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
452constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
453constexpr FeatureBitset ImpliedFeaturesCLWB = {};
454constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
455constexpr FeatureBitset ImpliedFeaturesCMOV = {};
456constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
457constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
458constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
459constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
460constexpr FeatureBitset ImpliedFeaturesFXSR = {};
461constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
462constexpr FeatureBitset ImpliedFeaturesLWP = {};
463constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
464constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
465constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
466constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
467constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
468constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
469constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
470constexpr FeatureBitset ImpliedFeaturesPKU = {};
471constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
472constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
473constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
474constexpr FeatureBitset ImpliedFeaturesRDPID = {};
475constexpr FeatureBitset ImpliedFeaturesRDRND = {};
476constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
477constexpr FeatureBitset ImpliedFeaturesRTM = {};
478constexpr FeatureBitset ImpliedFeaturesSAHF = {};
479constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
480constexpr FeatureBitset ImpliedFeaturesSGX = {};
481constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
482constexpr FeatureBitset ImpliedFeaturesTBM = {};
483constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
484constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
485constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
486constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
487constexpr FeatureBitset ImpliedFeaturesX87 = {};
488constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]489
490// Not really CPU features, but need to be in the table because clang uses
491// target features to communicate them to the backend.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]492constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
493constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
494constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
495constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
496constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]497
498// XSAVE features are dependent on basic XSAVE.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]499constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
500constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
501constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]502
503// MMX->3DNOW->3DNOWA chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]504constexpr FeatureBitset ImpliedFeaturesMMX = {};
505constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
506constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]507
508// SSE/AVX/AVX512F chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]509constexpr FeatureBitset ImpliedFeaturesSSE = {};
510constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
511constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
512constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
513constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
514constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
515constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
516constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
517constexpr FeatureBitset ImpliedFeaturesAVX512F =
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]518 FeatureAVX2 | FeatureF16C | FeatureFMA;
519
520// Vector extensions that build on SSE or AVX.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]521constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
522constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
523constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
524constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
525constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
526constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
527constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
528constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]529
530// AVX512 features.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]531constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
532constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
533constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
534constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
535constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
536constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]537
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]538constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
539constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
540constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
541constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
542constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
543constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
544constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
545constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]546
547// FIXME: These two aren't really implemented and just exist in the feature
548// list for __builtin_cpu_supports. So omit their dependencies.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]549constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
550constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]551
552// SSE4_A->FMA4->XOP chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]553constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
554constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
555constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]556
557// AMX Features
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]558constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
559constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
560constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]561
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]562// Key Locker Features
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]563constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
564constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]565
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]566constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]567#define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]568#include "llvm/Support/X86TargetParser.def"
569};
570
571void llvm::X86::getFeaturesForCPU(StringRef CPU,
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]572 SmallVectorImpl<StringRef> &EnabledFeatures) {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]573 auto I = llvm::find_if(Processors,
574 [&](const ProcInfo &P) { return P.Name == CPU; });
575 assert(I != std::end(Processors) && "Processor not found!");
576
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]577 FeatureBitset Bits = I->Features;
578
579 // Remove the 64-bit feature which we only use to validate if a CPU can
580 // be used with 64-bit mode.
581 Bits &= ~Feature64BIT;
582
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]583 // Add the string version of all set bits.
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]584 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
585 if (Bits[i] && !FeatureInfos[i].Name.empty())
586 EnabledFeatures.push_back(FeatureInfos[i].Name);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]587}
588
589// For each feature that is (transitively) implied by this feature, set it.
590static void getImpliedEnabledFeatures(FeatureBitset &Bits,
591 const FeatureBitset &Implies) {
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]592 // Fast path: Implies is often empty.
593 if (!Implies.any())
594 return;
595 FeatureBitset Prev;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]596 Bits |= Implies;
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]597 do {
598 Prev = Bits;
599 for (unsigned i = CPU_FEATURE_MAX; i;)
600 if (Bits[--i])
601 Bits |= FeatureInfos[i].ImpliedFeatures;
602 } while (Prev != Bits);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]603}
604
605/// Create bit vector of features that are implied disabled if the feature
606/// passed in Value is disabled.
607static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
608 // Check all features looking for any dependent on this feature. If we find
609 // one, mark it and recursively find any feature that depend on it.
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]610 FeatureBitset Prev;
611 Bits.set(Value);
612 do {
613 Prev = Bits;
614 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
615 if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
616 Bits.set(i);
617 } while (Prev != Bits);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]618}
619
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]620void llvm::X86::updateImpliedFeatures(
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]621 StringRef Feature, bool Enabled,
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]622 StringMap<bool> &Features) {
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]623 auto I = llvm::find_if(
624 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
625 if (I == std::end(FeatureInfos)) {
Craig Topper44ea81a2020-07-07 00:27:50 -0700[diff] [blame]626 // FIXME: This shouldn't happen, but may not have all features in the table
627 // yet.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]628 return;
629 }
630
631 FeatureBitset ImpliedBits;
632 if (Enabled)
633 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
634 else
635 getImpliedDisabledFeatures(ImpliedBits,
636 std::distance(std::begin(FeatureInfos), I));
637
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]638 // Update the map entry for all implied features.
639 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
640 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
641 Features[FeatureInfos[i].Name] = Enabled;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]642}