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gerrit-public.fairphone.software / toolchain / llvm-project / 01674939b2347b461adeca09398ef5e69b1717c4 / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: ca1ce057c011c8edb4e7f8fbc4fdb36ac1a35d7d [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]17#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]22#include "llvm/CodeGen/MachineJumpTableInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]23#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]24#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/DerivedTypes.h"
26#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]27#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]28#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]29#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]30#include "llvm/MC/MCExpr.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Target/TargetLoweringObjectFile.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]37#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]38#include <cctype>
39using namespace llvm;
40
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]41static cl::opt<bool> JumpIsExpensiveOverride(
42 "jump-is-expensive", cl::init(false),
43 cl::desc("Do not create extra branches to split comparison logic."),
44 cl::Hidden);
45
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]46/// InitLibcallNames - Set default libcall names.
47///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]48static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]49 Names[RTLIB::SHL_I16] = "__ashlhi3";
50 Names[RTLIB::SHL_I32] = "__ashlsi3";
51 Names[RTLIB::SHL_I64] = "__ashldi3";
52 Names[RTLIB::SHL_I128] = "__ashlti3";
53 Names[RTLIB::SRL_I16] = "__lshrhi3";
54 Names[RTLIB::SRL_I32] = "__lshrsi3";
55 Names[RTLIB::SRL_I64] = "__lshrdi3";
56 Names[RTLIB::SRL_I128] = "__lshrti3";
57 Names[RTLIB::SRA_I16] = "__ashrhi3";
58 Names[RTLIB::SRA_I32] = "__ashrsi3";
59 Names[RTLIB::SRA_I64] = "__ashrdi3";
60 Names[RTLIB::SRA_I128] = "__ashrti3";
61 Names[RTLIB::MUL_I8] = "__mulqi3";
62 Names[RTLIB::MUL_I16] = "__mulhi3";
63 Names[RTLIB::MUL_I32] = "__mulsi3";
64 Names[RTLIB::MUL_I64] = "__muldi3";
65 Names[RTLIB::MUL_I128] = "__multi3";
66 Names[RTLIB::MULO_I32] = "__mulosi4";
67 Names[RTLIB::MULO_I64] = "__mulodi4";
68 Names[RTLIB::MULO_I128] = "__muloti4";
69 Names[RTLIB::SDIV_I8] = "__divqi3";
70 Names[RTLIB::SDIV_I16] = "__divhi3";
71 Names[RTLIB::SDIV_I32] = "__divsi3";
72 Names[RTLIB::SDIV_I64] = "__divdi3";
73 Names[RTLIB::SDIV_I128] = "__divti3";
74 Names[RTLIB::UDIV_I8] = "__udivqi3";
75 Names[RTLIB::UDIV_I16] = "__udivhi3";
76 Names[RTLIB::UDIV_I32] = "__udivsi3";
77 Names[RTLIB::UDIV_I64] = "__udivdi3";
78 Names[RTLIB::UDIV_I128] = "__udivti3";
79 Names[RTLIB::SREM_I8] = "__modqi3";
80 Names[RTLIB::SREM_I16] = "__modhi3";
81 Names[RTLIB::SREM_I32] = "__modsi3";
82 Names[RTLIB::SREM_I64] = "__moddi3";
83 Names[RTLIB::SREM_I128] = "__modti3";
84 Names[RTLIB::UREM_I8] = "__umodqi3";
85 Names[RTLIB::UREM_I16] = "__umodhi3";
86 Names[RTLIB::UREM_I32] = "__umodsi3";
87 Names[RTLIB::UREM_I64] = "__umoddi3";
88 Names[RTLIB::UREM_I128] = "__umodti3";
89
90 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]91 Names[RTLIB::SDIVREM_I8] = nullptr;
92 Names[RTLIB::SDIVREM_I16] = nullptr;
93 Names[RTLIB::SDIVREM_I32] = nullptr;
94 Names[RTLIB::SDIVREM_I64] = nullptr;
95 Names[RTLIB::SDIVREM_I128] = nullptr;
96 Names[RTLIB::UDIVREM_I8] = nullptr;
97 Names[RTLIB::UDIVREM_I16] = nullptr;
98 Names[RTLIB::UDIVREM_I32] = nullptr;
99 Names[RTLIB::UDIVREM_I64] = nullptr;
100 Names[RTLIB::UDIVREM_I128] = nullptr;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]101
102 Names[RTLIB::NEG_I32] = "__negsi2";
103 Names[RTLIB::NEG_I64] = "__negdi2";
104 Names[RTLIB::ADD_F32] = "__addsf3";
105 Names[RTLIB::ADD_F64] = "__adddf3";
106 Names[RTLIB::ADD_F80] = "__addxf3";
107 Names[RTLIB::ADD_F128] = "__addtf3";
108 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
109 Names[RTLIB::SUB_F32] = "__subsf3";
110 Names[RTLIB::SUB_F64] = "__subdf3";
111 Names[RTLIB::SUB_F80] = "__subxf3";
112 Names[RTLIB::SUB_F128] = "__subtf3";
113 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
114 Names[RTLIB::MUL_F32] = "__mulsf3";
115 Names[RTLIB::MUL_F64] = "__muldf3";
116 Names[RTLIB::MUL_F80] = "__mulxf3";
117 Names[RTLIB::MUL_F128] = "__multf3";
118 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
119 Names[RTLIB::DIV_F32] = "__divsf3";
120 Names[RTLIB::DIV_F64] = "__divdf3";
121 Names[RTLIB::DIV_F80] = "__divxf3";
122 Names[RTLIB::DIV_F128] = "__divtf3";
123 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
124 Names[RTLIB::REM_F32] = "fmodf";
125 Names[RTLIB::REM_F64] = "fmod";
126 Names[RTLIB::REM_F80] = "fmodl";
127 Names[RTLIB::REM_F128] = "fmodl";
128 Names[RTLIB::REM_PPCF128] = "fmodl";
129 Names[RTLIB::FMA_F32] = "fmaf";
130 Names[RTLIB::FMA_F64] = "fma";
131 Names[RTLIB::FMA_F80] = "fmal";
132 Names[RTLIB::FMA_F128] = "fmal";
133 Names[RTLIB::FMA_PPCF128] = "fmal";
134 Names[RTLIB::POWI_F32] = "__powisf2";
135 Names[RTLIB::POWI_F64] = "__powidf2";
136 Names[RTLIB::POWI_F80] = "__powixf2";
137 Names[RTLIB::POWI_F128] = "__powitf2";
138 Names[RTLIB::POWI_PPCF128] = "__powitf2";
139 Names[RTLIB::SQRT_F32] = "sqrtf";
140 Names[RTLIB::SQRT_F64] = "sqrt";
141 Names[RTLIB::SQRT_F80] = "sqrtl";
142 Names[RTLIB::SQRT_F128] = "sqrtl";
143 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
144 Names[RTLIB::LOG_F32] = "logf";
145 Names[RTLIB::LOG_F64] = "log";
146 Names[RTLIB::LOG_F80] = "logl";
147 Names[RTLIB::LOG_F128] = "logl";
148 Names[RTLIB::LOG_PPCF128] = "logl";
149 Names[RTLIB::LOG2_F32] = "log2f";
150 Names[RTLIB::LOG2_F64] = "log2";
151 Names[RTLIB::LOG2_F80] = "log2l";
152 Names[RTLIB::LOG2_F128] = "log2l";
153 Names[RTLIB::LOG2_PPCF128] = "log2l";
154 Names[RTLIB::LOG10_F32] = "log10f";
155 Names[RTLIB::LOG10_F64] = "log10";
156 Names[RTLIB::LOG10_F80] = "log10l";
157 Names[RTLIB::LOG10_F128] = "log10l";
158 Names[RTLIB::LOG10_PPCF128] = "log10l";
159 Names[RTLIB::EXP_F32] = "expf";
160 Names[RTLIB::EXP_F64] = "exp";
161 Names[RTLIB::EXP_F80] = "expl";
162 Names[RTLIB::EXP_F128] = "expl";
163 Names[RTLIB::EXP_PPCF128] = "expl";
164 Names[RTLIB::EXP2_F32] = "exp2f";
165 Names[RTLIB::EXP2_F64] = "exp2";
166 Names[RTLIB::EXP2_F80] = "exp2l";
167 Names[RTLIB::EXP2_F128] = "exp2l";
168 Names[RTLIB::EXP2_PPCF128] = "exp2l";
169 Names[RTLIB::SIN_F32] = "sinf";
170 Names[RTLIB::SIN_F64] = "sin";
171 Names[RTLIB::SIN_F80] = "sinl";
172 Names[RTLIB::SIN_F128] = "sinl";
173 Names[RTLIB::SIN_PPCF128] = "sinl";
174 Names[RTLIB::COS_F32] = "cosf";
175 Names[RTLIB::COS_F64] = "cos";
176 Names[RTLIB::COS_F80] = "cosl";
177 Names[RTLIB::COS_F128] = "cosl";
178 Names[RTLIB::COS_PPCF128] = "cosl";
179 Names[RTLIB::POW_F32] = "powf";
180 Names[RTLIB::POW_F64] = "pow";
181 Names[RTLIB::POW_F80] = "powl";
182 Names[RTLIB::POW_F128] = "powl";
183 Names[RTLIB::POW_PPCF128] = "powl";
184 Names[RTLIB::CEIL_F32] = "ceilf";
185 Names[RTLIB::CEIL_F64] = "ceil";
186 Names[RTLIB::CEIL_F80] = "ceill";
187 Names[RTLIB::CEIL_F128] = "ceill";
188 Names[RTLIB::CEIL_PPCF128] = "ceill";
189 Names[RTLIB::TRUNC_F32] = "truncf";
190 Names[RTLIB::TRUNC_F64] = "trunc";
191 Names[RTLIB::TRUNC_F80] = "truncl";
192 Names[RTLIB::TRUNC_F128] = "truncl";
193 Names[RTLIB::TRUNC_PPCF128] = "truncl";
194 Names[RTLIB::RINT_F32] = "rintf";
195 Names[RTLIB::RINT_F64] = "rint";
196 Names[RTLIB::RINT_F80] = "rintl";
197 Names[RTLIB::RINT_F128] = "rintl";
198 Names[RTLIB::RINT_PPCF128] = "rintl";
199 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
200 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
201 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
202 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
203 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]204 Names[RTLIB::ROUND_F32] = "roundf";
205 Names[RTLIB::ROUND_F64] = "round";
206 Names[RTLIB::ROUND_F80] = "roundl";
207 Names[RTLIB::ROUND_F128] = "roundl";
208 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]209 Names[RTLIB::FLOOR_F32] = "floorf";
210 Names[RTLIB::FLOOR_F64] = "floor";
211 Names[RTLIB::FLOOR_F80] = "floorl";
212 Names[RTLIB::FLOOR_F128] = "floorl";
213 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]214 Names[RTLIB::FMIN_F32] = "fminf";
215 Names[RTLIB::FMIN_F64] = "fmin";
216 Names[RTLIB::FMIN_F80] = "fminl";
217 Names[RTLIB::FMIN_F128] = "fminl";
218 Names[RTLIB::FMIN_PPCF128] = "fminl";
219 Names[RTLIB::FMAX_F32] = "fmaxf";
220 Names[RTLIB::FMAX_F64] = "fmax";
221 Names[RTLIB::FMAX_F80] = "fmaxl";
222 Names[RTLIB::FMAX_F128] = "fmaxl";
223 Names[RTLIB::FMAX_PPCF128] = "fmaxl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]224 Names[RTLIB::ROUND_F32] = "roundf";
225 Names[RTLIB::ROUND_F64] = "round";
226 Names[RTLIB::ROUND_F80] = "roundl";
227 Names[RTLIB::ROUND_F128] = "roundl";
228 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]229 Names[RTLIB::COPYSIGN_F32] = "copysignf";
230 Names[RTLIB::COPYSIGN_F64] = "copysign";
231 Names[RTLIB::COPYSIGN_F80] = "copysignl";
232 Names[RTLIB::COPYSIGN_F128] = "copysignl";
233 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]234 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq";
235 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]236 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
237 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
238 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
239 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
240 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]241 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
242 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
243 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
244 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]245 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
246 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
247 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]248 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]249 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
250 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]251 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]252 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
253 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
254 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]255 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
256 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
257 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
258 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
259 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
260 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
261 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
262 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
263 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]264 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]265 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
266 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]267 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
268 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
269 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]270 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
271 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
272 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
273 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
274 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
275 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
276 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
277 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
278 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
279 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
280 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
281 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
282 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
283 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
284 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
285 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]286 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]287 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
288 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
289 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
290 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
291 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
292 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
293 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
294 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
295 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
296 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
297 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
298 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
299 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
300 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]301 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]302 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
303 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
304 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
305 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
306 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
307 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
308 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
309 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
310 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
311 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
312 Names[RTLIB::OEQ_F32] = "__eqsf2";
313 Names[RTLIB::OEQ_F64] = "__eqdf2";
314 Names[RTLIB::OEQ_F128] = "__eqtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]315 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]316 Names[RTLIB::UNE_F32] = "__nesf2";
317 Names[RTLIB::UNE_F64] = "__nedf2";
318 Names[RTLIB::UNE_F128] = "__netf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]319 Names[RTLIB::UNE_PPCF128] = "__gcc_qne";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]320 Names[RTLIB::OGE_F32] = "__gesf2";
321 Names[RTLIB::OGE_F64] = "__gedf2";
322 Names[RTLIB::OGE_F128] = "__getf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]323 Names[RTLIB::OGE_PPCF128] = "__gcc_qge";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]324 Names[RTLIB::OLT_F32] = "__ltsf2";
325 Names[RTLIB::OLT_F64] = "__ltdf2";
326 Names[RTLIB::OLT_F128] = "__lttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]327 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]328 Names[RTLIB::OLE_F32] = "__lesf2";
329 Names[RTLIB::OLE_F64] = "__ledf2";
330 Names[RTLIB::OLE_F128] = "__letf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]331 Names[RTLIB::OLE_PPCF128] = "__gcc_qle";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]332 Names[RTLIB::OGT_F32] = "__gtsf2";
333 Names[RTLIB::OGT_F64] = "__gtdf2";
334 Names[RTLIB::OGT_F128] = "__gttf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]335 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]336 Names[RTLIB::UO_F32] = "__unordsf2";
337 Names[RTLIB::UO_F64] = "__unorddf2";
338 Names[RTLIB::UO_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]339 Names[RTLIB::UO_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]340 Names[RTLIB::O_F32] = "__unordsf2";
341 Names[RTLIB::O_F64] = "__unorddf2";
342 Names[RTLIB::O_F128] = "__unordtf2";
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]343 Names[RTLIB::O_PPCF128] = "__gcc_qunord";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]344 Names[RTLIB::MEMCPY] = "memcpy";
345 Names[RTLIB::MEMMOVE] = "memmove";
346 Names[RTLIB::MEMSET] = "memset";
347 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
348 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
349 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
350 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
351 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]352 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]353 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
354 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
355 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
356 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]357 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]358 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
359 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
360 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
361 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]362 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]363 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
364 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
365 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
366 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]367 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]368 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
369 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
370 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
371 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]372 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]373 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
374 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
375 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
376 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]377 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]378 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
379 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
380 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
381 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]382 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]383 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
384 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
385 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
386 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]387 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]388 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
389 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
390 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
391 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
392 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
393 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
394 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
395 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
396 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
397 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
398 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
399 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
400 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
401 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
402 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
403 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
404 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
405 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
406 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
407 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
Evan Cheng0e88c7d2013-01-29 02:32:37 +0000[diff] [blame]408
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]409 if (TT.getEnvironment() == Triple::GNU) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]410 Names[RTLIB::SINCOS_F32] = "sincosf";
411 Names[RTLIB::SINCOS_F64] = "sincos";
412 Names[RTLIB::SINCOS_F80] = "sincosl";
413 Names[RTLIB::SINCOS_F128] = "sincosl";
414 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
415 } else {
416 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]417 Names[RTLIB::SINCOS_F32] = nullptr;
418 Names[RTLIB::SINCOS_F64] = nullptr;
419 Names[RTLIB::SINCOS_F80] = nullptr;
420 Names[RTLIB::SINCOS_F128] = nullptr;
421 Names[RTLIB::SINCOS_PPCF128] = nullptr;
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]422 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]423
Simon Pilgrim2bfd9122014-11-29 19:18:21 +0000[diff] [blame]424 if (!TT.isOSOpenBSD()) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]425 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
426 } else {
427 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]428 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr;
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]429 }
Ahmed Bougacha6402ad22015-05-14 01:00:51 +0000[diff] [blame]430
431 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
432 // of the gnueabi-style __gnu_*_ieee.
433 // FIXME: What about other targets?
434 if (TT.isOSDarwin()) {
435 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2";
436 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2";
437 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]438}
439
440/// InitLibcallCallingConvs - Set default libcall CallingConvs.
441///
442static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
443 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
444 CCs[i] = CallingConv::C;
445 }
446}
447
448/// getFPEXT - Return the FPEXT_*_* value for the given types, or
449/// UNKNOWN_LIBCALL if there is none.
450RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame]451 if (OpVT == MVT::f16) {
452 if (RetVT == MVT::f32)
453 return FPEXT_F16_F32;
454 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]455 if (RetVT == MVT::f64)
456 return FPEXT_F32_F64;
457 if (RetVT == MVT::f128)
458 return FPEXT_F32_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]459 if (RetVT == MVT::ppcf128)
460 return FPEXT_F32_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]461 } else if (OpVT == MVT::f64) {
462 if (RetVT == MVT::f128)
463 return FPEXT_F64_F128;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]464 else if (RetVT == MVT::ppcf128)
465 return FPEXT_F64_PPCF128;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]466 }
467
468 return UNKNOWN_LIBCALL;
469}
470
471/// getFPROUND - Return the FPROUND_*_* value for the given types, or
472/// UNKNOWN_LIBCALL if there is none.
473RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]474 if (RetVT == MVT::f16) {
475 if (OpVT == MVT::f32)
476 return FPROUND_F32_F16;
477 if (OpVT == MVT::f64)
478 return FPROUND_F64_F16;
479 if (OpVT == MVT::f80)
480 return FPROUND_F80_F16;
481 if (OpVT == MVT::f128)
482 return FPROUND_F128_F16;
483 if (OpVT == MVT::ppcf128)
484 return FPROUND_PPCF128_F16;
485 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]486 if (OpVT == MVT::f64)
487 return FPROUND_F64_F32;
488 if (OpVT == MVT::f80)
489 return FPROUND_F80_F32;
490 if (OpVT == MVT::f128)
491 return FPROUND_F128_F32;
492 if (OpVT == MVT::ppcf128)
493 return FPROUND_PPCF128_F32;
494 } else if (RetVT == MVT::f64) {
495 if (OpVT == MVT::f80)
496 return FPROUND_F80_F64;
497 if (OpVT == MVT::f128)
498 return FPROUND_F128_F64;
499 if (OpVT == MVT::ppcf128)
500 return FPROUND_PPCF128_F64;
501 }
502
503 return UNKNOWN_LIBCALL;
504}
505
506/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
507/// UNKNOWN_LIBCALL if there is none.
508RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
509 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]510 if (RetVT == MVT::i32)
511 return FPTOSINT_F32_I32;
512 if (RetVT == MVT::i64)
513 return FPTOSINT_F32_I64;
514 if (RetVT == MVT::i128)
515 return FPTOSINT_F32_I128;
516 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]517 if (RetVT == MVT::i32)
518 return FPTOSINT_F64_I32;
519 if (RetVT == MVT::i64)
520 return FPTOSINT_F64_I64;
521 if (RetVT == MVT::i128)
522 return FPTOSINT_F64_I128;
523 } else if (OpVT == MVT::f80) {
524 if (RetVT == MVT::i32)
525 return FPTOSINT_F80_I32;
526 if (RetVT == MVT::i64)
527 return FPTOSINT_F80_I64;
528 if (RetVT == MVT::i128)
529 return FPTOSINT_F80_I128;
530 } else if (OpVT == MVT::f128) {
531 if (RetVT == MVT::i32)
532 return FPTOSINT_F128_I32;
533 if (RetVT == MVT::i64)
534 return FPTOSINT_F128_I64;
535 if (RetVT == MVT::i128)
536 return FPTOSINT_F128_I128;
537 } else if (OpVT == MVT::ppcf128) {
538 if (RetVT == MVT::i32)
539 return FPTOSINT_PPCF128_I32;
540 if (RetVT == MVT::i64)
541 return FPTOSINT_PPCF128_I64;
542 if (RetVT == MVT::i128)
543 return FPTOSINT_PPCF128_I128;
544 }
545 return UNKNOWN_LIBCALL;
546}
547
548/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
549/// UNKNOWN_LIBCALL if there is none.
550RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
551 if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]552 if (RetVT == MVT::i32)
553 return FPTOUINT_F32_I32;
554 if (RetVT == MVT::i64)
555 return FPTOUINT_F32_I64;
556 if (RetVT == MVT::i128)
557 return FPTOUINT_F32_I128;
558 } else if (OpVT == MVT::f64) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]559 if (RetVT == MVT::i32)
560 return FPTOUINT_F64_I32;
561 if (RetVT == MVT::i64)
562 return FPTOUINT_F64_I64;
563 if (RetVT == MVT::i128)
564 return FPTOUINT_F64_I128;
565 } else if (OpVT == MVT::f80) {
566 if (RetVT == MVT::i32)
567 return FPTOUINT_F80_I32;
568 if (RetVT == MVT::i64)
569 return FPTOUINT_F80_I64;
570 if (RetVT == MVT::i128)
571 return FPTOUINT_F80_I128;
572 } else if (OpVT == MVT::f128) {
573 if (RetVT == MVT::i32)
574 return FPTOUINT_F128_I32;
575 if (RetVT == MVT::i64)
576 return FPTOUINT_F128_I64;
577 if (RetVT == MVT::i128)
578 return FPTOUINT_F128_I128;
579 } else if (OpVT == MVT::ppcf128) {
580 if (RetVT == MVT::i32)
581 return FPTOUINT_PPCF128_I32;
582 if (RetVT == MVT::i64)
583 return FPTOUINT_PPCF128_I64;
584 if (RetVT == MVT::i128)
585 return FPTOUINT_PPCF128_I128;
586 }
587 return UNKNOWN_LIBCALL;
588}
589
590/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
591/// UNKNOWN_LIBCALL if there is none.
592RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
593 if (OpVT == MVT::i32) {
594 if (RetVT == MVT::f32)
595 return SINTTOFP_I32_F32;
596 if (RetVT == MVT::f64)
597 return SINTTOFP_I32_F64;
598 if (RetVT == MVT::f80)
599 return SINTTOFP_I32_F80;
600 if (RetVT == MVT::f128)
601 return SINTTOFP_I32_F128;
602 if (RetVT == MVT::ppcf128)
603 return SINTTOFP_I32_PPCF128;
604 } else if (OpVT == MVT::i64) {
605 if (RetVT == MVT::f32)
606 return SINTTOFP_I64_F32;
607 if (RetVT == MVT::f64)
608 return SINTTOFP_I64_F64;
609 if (RetVT == MVT::f80)
610 return SINTTOFP_I64_F80;
611 if (RetVT == MVT::f128)
612 return SINTTOFP_I64_F128;
613 if (RetVT == MVT::ppcf128)
614 return SINTTOFP_I64_PPCF128;
615 } else if (OpVT == MVT::i128) {
616 if (RetVT == MVT::f32)
617 return SINTTOFP_I128_F32;
618 if (RetVT == MVT::f64)
619 return SINTTOFP_I128_F64;
620 if (RetVT == MVT::f80)
621 return SINTTOFP_I128_F80;
622 if (RetVT == MVT::f128)
623 return SINTTOFP_I128_F128;
624 if (RetVT == MVT::ppcf128)
625 return SINTTOFP_I128_PPCF128;
626 }
627 return UNKNOWN_LIBCALL;
628}
629
630/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
631/// UNKNOWN_LIBCALL if there is none.
632RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
633 if (OpVT == MVT::i32) {
634 if (RetVT == MVT::f32)
635 return UINTTOFP_I32_F32;
636 if (RetVT == MVT::f64)
637 return UINTTOFP_I32_F64;
638 if (RetVT == MVT::f80)
639 return UINTTOFP_I32_F80;
640 if (RetVT == MVT::f128)
641 return UINTTOFP_I32_F128;
642 if (RetVT == MVT::ppcf128)
643 return UINTTOFP_I32_PPCF128;
644 } else if (OpVT == MVT::i64) {
645 if (RetVT == MVT::f32)
646 return UINTTOFP_I64_F32;
647 if (RetVT == MVT::f64)
648 return UINTTOFP_I64_F64;
649 if (RetVT == MVT::f80)
650 return UINTTOFP_I64_F80;
651 if (RetVT == MVT::f128)
652 return UINTTOFP_I64_F128;
653 if (RetVT == MVT::ppcf128)
654 return UINTTOFP_I64_PPCF128;
655 } else if (OpVT == MVT::i128) {
656 if (RetVT == MVT::f32)
657 return UINTTOFP_I128_F32;
658 if (RetVT == MVT::f64)
659 return UINTTOFP_I128_F64;
660 if (RetVT == MVT::f80)
661 return UINTTOFP_I128_F80;
662 if (RetVT == MVT::f128)
663 return UINTTOFP_I128_F128;
664 if (RetVT == MVT::ppcf128)
665 return UINTTOFP_I128_PPCF128;
666 }
667 return UNKNOWN_LIBCALL;
668}
669
Benjamin Kramerc54c38e2015-03-05 20:04:29 +0000[diff] [blame]670RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) {
671#define OP_TO_LIBCALL(Name, Enum) \
672 case Name: \
673 switch (VT.SimpleTy) { \
674 default: \
675 return UNKNOWN_LIBCALL; \
676 case MVT::i8: \
677 return Enum##_1; \
678 case MVT::i16: \
679 return Enum##_2; \
680 case MVT::i32: \
681 return Enum##_4; \
682 case MVT::i64: \
683 return Enum##_8; \
684 case MVT::i128: \
685 return Enum##_16; \
686 }
687
688 switch (Opc) {
689 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
690 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
691 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
692 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
693 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
694 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
695 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
696 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
697 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
698 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
699 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
700 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
701 }
702
703#undef OP_TO_LIBCALL
704
705 return UNKNOWN_LIBCALL;
706}
707
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]708/// InitCmpLibcallCCs - Set default comparison libcall CC.
709///
710static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
711 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
712 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
713 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
714 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]715 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]716 CCs[RTLIB::UNE_F32] = ISD::SETNE;
717 CCs[RTLIB::UNE_F64] = ISD::SETNE;
718 CCs[RTLIB::UNE_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]719 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]720 CCs[RTLIB::OGE_F32] = ISD::SETGE;
721 CCs[RTLIB::OGE_F64] = ISD::SETGE;
722 CCs[RTLIB::OGE_F128] = ISD::SETGE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]723 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]724 CCs[RTLIB::OLT_F32] = ISD::SETLT;
725 CCs[RTLIB::OLT_F64] = ISD::SETLT;
726 CCs[RTLIB::OLT_F128] = ISD::SETLT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]727 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]728 CCs[RTLIB::OLE_F32] = ISD::SETLE;
729 CCs[RTLIB::OLE_F64] = ISD::SETLE;
730 CCs[RTLIB::OLE_F128] = ISD::SETLE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]731 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]732 CCs[RTLIB::OGT_F32] = ISD::SETGT;
733 CCs[RTLIB::OGT_F64] = ISD::SETGT;
734 CCs[RTLIB::OGT_F128] = ISD::SETGT;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]735 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]736 CCs[RTLIB::UO_F32] = ISD::SETNE;
737 CCs[RTLIB::UO_F64] = ISD::SETNE;
738 CCs[RTLIB::UO_F128] = ISD::SETNE;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]739 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]740 CCs[RTLIB::O_F32] = ISD::SETEQ;
741 CCs[RTLIB::O_F64] = ISD::SETEQ;
742 CCs[RTLIB::O_F128] = ISD::SETEQ;
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]743 CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]744}
745
Aditya Nandakumar30531552014-11-13 21:29:21 +0000[diff] [blame]746/// NOTE: The TargetMachine owns TLOF.
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]747TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]748 initActions();
749
750 // Perform these initializations only once.
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]751 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
752 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
753 = MaxStoresPerMemmoveOptSize = 4;
754 UseUnderscoreSetJmp = false;
755 UseUnderscoreLongJmp = false;
756 SelectIsExpensive = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]757 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]758 HasExtractBitsInsn = false;
Matt Arsenaultbf0db912015-01-13 20:53:23 +0000[diff] [blame]759 FsqrtIsCheap = false;
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]760 JumpIsExpensive = JumpIsExpensiveOverride;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]761 PredictableSelectIsExpensive = false;
Tim Northovercea0abb2014-03-29 08:22:29 +0000[diff] [blame]762 MaskAndBranchFoldingIsLegal = false;
Quentin Colombetfc2201e2014-12-17 01:36:17 +0000[diff] [blame]763 EnableExtLdPromotion = false;
Pedro Artigascaa56582014-08-08 16:46:53 +0000[diff] [blame]764 HasFloatingPointExceptions = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]765 StackPointerRegisterToSaveRestore = 0;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]766 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]767 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]768 BooleanVectorContents = UndefinedBooleanContent;
769 SchedPreferenceInfo = Sched::ILP;
770 JumpBufSize = 0;
771 JumpBufAlignment = 0;
772 MinFunctionAlignment = 0;
773 PrefFunctionAlignment = 0;
774 PrefLoopAlignment = 0;
Matt Arsenaultd8fed1b2015-11-11 18:44:33 +0000[diff] [blame]775 GatherAllAliasesMaxDepth = 6;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]776 MinStackArgumentAlignment = 1;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]777 InsertFencesForAtomic = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]778 MinimumJumpTableEntries = 4;
779
Daniel Sanders110bf6d2015-06-24 13:25:57 +0000[diff] [blame]780 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple());
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]781 InitCmpLibcallCCs(CmpLibcallCCs);
782 InitLibcallCallingConvs(LibcallCallingConvs);
783}
784
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]785void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]786 // All operations default to being supported.
787 memset(OpActions, 0, sizeof(OpActions));
788 memset(LoadExtActions, 0, sizeof(LoadExtActions));
789 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
790 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
791 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]792 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
793 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]794
795 // Set default actions for various operations.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]796 for (MVT VT : MVT::all_valuetypes()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]797 // Default all indexed load / store to expand.
798 for (unsigned IM = (unsigned)ISD::PRE_INC;
799 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]800 setIndexedLoadAction(IM, VT, Expand);
801 setIndexedStoreAction(IM, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]802 }
803
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]804 // Most backends expect to see the node which just returns the value loaded.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]805 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]806
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]807 // These operations default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]808 setOperationAction(ISD::FGETSIGN, VT, Expand);
809 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
810 setOperationAction(ISD::FMINNUM, VT, Expand);
811 setOperationAction(ISD::FMAXNUM, VT, Expand);
James Molloy01cdecc2015-08-11 09:13:05 +0000[diff] [blame]812 setOperationAction(ISD::FMINNAN, VT, Expand);
813 setOperationAction(ISD::FMAXNAN, VT, Expand);
Matt Arsenault0dc54c42015-02-20 22:10:33 +0000[diff] [blame]814 setOperationAction(ISD::FMAD, VT, Expand);
James Molloy7e9776b2015-05-15 09:03:15 +0000[diff] [blame]815 setOperationAction(ISD::SMIN, VT, Expand);
816 setOperationAction(ISD::SMAX, VT, Expand);
817 setOperationAction(ISD::UMIN, VT, Expand);
818 setOperationAction(ISD::UMAX, VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]819
Jan Vesely75395482015-04-29 16:30:46 +0000[diff] [blame]820 // Overflow operations default to expand
821 setOperationAction(ISD::SADDO, VT, Expand);
822 setOperationAction(ISD::SSUBO, VT, Expand);
823 setOperationAction(ISD::UADDO, VT, Expand);
824 setOperationAction(ISD::USUBO, VT, Expand);
825 setOperationAction(ISD::SMULO, VT, Expand);
826 setOperationAction(ISD::UMULO, VT, Expand);
Hal Finkelcd8664c2015-12-11 23:11:52 +0000[diff] [blame]827
James Molloy90111f72015-11-12 12:29:09 +0000[diff] [blame]828 setOperationAction(ISD::BITREVERSE, VT, Expand);
829
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]830 // These library functions default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]831 setOperationAction(ISD::FROUND, VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]832
833 // These operations default to expand for vector types.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]834 if (VT.isVector()) {
835 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
836 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
837 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
838 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]839 }
Yury Gribovd7dbb662015-12-01 11:40:55 +0000[diff] [blame]840
841 // For most targets @llvm.get.dynamic.area.offest just returns 0.
842 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]843 }
844
845 // Most targets ignore the @llvm.prefetch intrinsic.
846 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
847
Ahmed Bougachaf9c19da2015-08-28 01:49:59 +0000[diff] [blame]848 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
849 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
850
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]851 // ConstantFP nodes default to expand. Targets can either change this to
852 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
853 // to optimize expansions for certain constants.
854 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
855 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
856 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
857 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
858 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
859
860 // These library functions default to expand.
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]861 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
862 setOperationAction(ISD::FLOG , VT, Expand);
863 setOperationAction(ISD::FLOG2, VT, Expand);
864 setOperationAction(ISD::FLOG10, VT, Expand);
865 setOperationAction(ISD::FEXP , VT, Expand);
866 setOperationAction(ISD::FEXP2, VT, Expand);
867 setOperationAction(ISD::FFLOOR, VT, Expand);
868 setOperationAction(ISD::FMINNUM, VT, Expand);
869 setOperationAction(ISD::FMAXNUM, VT, Expand);
870 setOperationAction(ISD::FNEARBYINT, VT, Expand);
871 setOperationAction(ISD::FCEIL, VT, Expand);
872 setOperationAction(ISD::FRINT, VT, Expand);
873 setOperationAction(ISD::FTRUNC, VT, Expand);
874 setOperationAction(ISD::FROUND, VT, Expand);
875 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]876
877 // Default ISD::TRAP to expand (which turns it into abort).
878 setOperationAction(ISD::TRAP, MVT::Other, Expand);
879
880 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
881 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
882 //
883 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]884}
885
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]886MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
887 EVT) const {
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]888 return MVT::getIntegerVT(8 * DL.getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]889}
890
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]891EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
892 const DataLayout &DL) const {
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]893 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
894 if (LHSTy.isVector())
895 return LHSTy;
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]896 return getScalarShiftAmountTy(DL, LHSTy);
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]897}
898
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]899/// canOpTrap - Returns true if the operation can trap for the value type.
900/// VT must be a legal type.
901bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
902 assert(isTypeLegal(VT));
903 switch (Op) {
904 default:
905 return false;
906 case ISD::FDIV:
907 case ISD::FREM:
908 case ISD::SDIV:
909 case ISD::UDIV:
910 case ISD::SREM:
911 case ISD::UREM:
912 return true;
913 }
914}
915
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]916void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
917 // If the command-line option was specified, ignore this request.
918 if (!JumpIsExpensiveOverride.getNumOccurrences())
919 JumpIsExpensive = isExpensive;
920}
921
Eric Christopher75dbd7c2015-02-25 22:41:30 +0000[diff] [blame]922TargetLoweringBase::LegalizeKind
923TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
924 // If this is a simple type, use the ComputeRegisterProp mechanism.
925 if (VT.isSimple()) {
926 MVT SVT = VT.getSimpleVT();
927 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
928 MVT NVT = TransformToType[SVT.SimpleTy];
929 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
930
931 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
932 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
933 "Promote may not follow Expand or Promote");
934
935 if (LA == TypeSplitVector)
936 return LegalizeKind(LA,
937 EVT::getVectorVT(Context, SVT.getVectorElementType(),
938 SVT.getVectorNumElements() / 2));
939 if (LA == TypeScalarizeVector)
940 return LegalizeKind(LA, SVT.getVectorElementType());
941 return LegalizeKind(LA, NVT);
942 }
943
944 // Handle Extended Scalar Types.
945 if (!VT.isVector()) {
946 assert(VT.isInteger() && "Float types must be simple");
947 unsigned BitSize = VT.getSizeInBits();
948 // First promote to a power-of-two size, then expand if necessary.
949 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
950 EVT NVT = VT.getRoundIntegerType(Context);
951 assert(NVT != VT && "Unable to round integer VT");
952 LegalizeKind NextStep = getTypeConversion(Context, NVT);
953 // Avoid multi-step promotion.
954 if (NextStep.first == TypePromoteInteger)
955 return NextStep;
956 // Return rounded integer type.
957 return LegalizeKind(TypePromoteInteger, NVT);
958 }
959
960 return LegalizeKind(TypeExpandInteger,
961 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
962 }
963
964 // Handle vector types.
965 unsigned NumElts = VT.getVectorNumElements();
966 EVT EltVT = VT.getVectorElementType();
967
968 // Vectors with only one element are always scalarized.
969 if (NumElts == 1)
970 return LegalizeKind(TypeScalarizeVector, EltVT);
971
972 // Try to widen vector elements until the element type is a power of two and
973 // promote it to a legal type later on, for example:
974 // <3 x i8> -> <4 x i8> -> <4 x i32>
975 if (EltVT.isInteger()) {
976 // Vectors with a number of elements that is not a power of two are always
977 // widened, for example <3 x i8> -> <4 x i8>.
978 if (!VT.isPow2VectorType()) {
979 NumElts = (unsigned)NextPowerOf2(NumElts);
980 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
981 return LegalizeKind(TypeWidenVector, NVT);
982 }
983
984 // Examine the element type.
985 LegalizeKind LK = getTypeConversion(Context, EltVT);
986
987 // If type is to be expanded, split the vector.
988 // <4 x i140> -> <2 x i140>
989 if (LK.first == TypeExpandInteger)
990 return LegalizeKind(TypeSplitVector,
991 EVT::getVectorVT(Context, EltVT, NumElts / 2));
992
993 // Promote the integer element types until a legal vector type is found
994 // or until the element integer type is too big. If a legal type was not
995 // found, fallback to the usual mechanism of widening/splitting the
996 // vector.
997 EVT OldEltVT = EltVT;
998 while (1) {
999 // Increase the bitwidth of the element to the next pow-of-two
1000 // (which is greater than 8 bits).
1001 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1002 .getRoundIntegerType(Context);
1003
1004 // Stop trying when getting a non-simple element type.
1005 // Note that vector elements may be greater than legal vector element
1006 // types. Example: X86 XMM registers hold 64bit element on 32bit
1007 // systems.
1008 if (!EltVT.isSimple())
1009 break;
1010
1011 // Build a new vector type and check if it is legal.
1012 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1013 // Found a legal promoted vector type.
1014 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1015 return LegalizeKind(TypePromoteInteger,
1016 EVT::getVectorVT(Context, EltVT, NumElts));
1017 }
1018
1019 // Reset the type to the unexpanded type if we did not find a legal vector
1020 // type with a promoted vector element type.
1021 EltVT = OldEltVT;
1022 }
1023
1024 // Try to widen the vector until a legal type is found.
1025 // If there is no wider legal type, split the vector.
1026 while (1) {
1027 // Round up to the next power of 2.
1028 NumElts = (unsigned)NextPowerOf2(NumElts);
1029
1030 // If there is no simple vector type with this many elements then there
1031 // cannot be a larger legal vector type. Note that this assumes that
1032 // there are no skipped intermediate vector types in the simple types.
1033 if (!EltVT.isSimple())
1034 break;
1035 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1036 if (LargerVector == MVT())
1037 break;
1038
1039 // If this type is legal then widen the vector.
1040 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1041 return LegalizeKind(TypeWidenVector, LargerVector);
1042 }
1043
1044 // Widen odd vectors to next power of two.
1045 if (!VT.isPow2VectorType()) {
1046 EVT NVT = VT.getPow2VectorType(Context);
1047 return LegalizeKind(TypeWidenVector, NVT);
1048 }
1049
1050 // Vectors with illegal element types are expanded.
1051 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1052 return LegalizeKind(TypeSplitVector, NVT);
1053}
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1054
1055static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1056 unsigned &NumIntermediates,
1057 MVT &RegisterVT,
1058 TargetLoweringBase *TLI) {
1059 // Figure out the right, legal destination reg to copy into.
1060 unsigned NumElts = VT.getVectorNumElements();
1061 MVT EltTy = VT.getVectorElementType();
1062
1063 unsigned NumVectorRegs = 1;
1064
1065 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1066 // could break down into LHS/RHS like LegalizeDAG does.
1067 if (!isPowerOf2_32(NumElts)) {
1068 NumVectorRegs = NumElts;
1069 NumElts = 1;
1070 }
1071
1072 // Divide the input until we get to a supported size. This will always
1073 // end with a scalar if the target doesn't support vectors.
1074 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
1075 NumElts >>= 1;
1076 NumVectorRegs <<= 1;
1077 }
1078
1079 NumIntermediates = NumVectorRegs;
1080
1081 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
1082 if (!TLI->isTypeLegal(NewVT))
1083 NewVT = EltTy;
1084 IntermediateVT = NewVT;
1085
1086 unsigned NewVTSize = NewVT.getSizeInBits();
1087
1088 // Convert sizes such as i33 to i64.
1089 if (!isPowerOf2_32(NewVTSize))
1090 NewVTSize = NextPowerOf2(NewVTSize);
1091
1092 MVT DestVT = TLI->getRegisterType(NewVT);
1093 RegisterVT = DestVT;
1094 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1095 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1096
1097 // Otherwise, promotion or legal types use the same number of registers as
1098 // the vector decimated to the appropriate level.
1099 return NumVectorRegs;
1100}
1101
1102/// isLegalRC - Return true if the value types that can be represented by the
1103/// specified register class are all legal.
1104bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
1105 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1106 I != E; ++I) {
1107 if (isTypeLegal(*I))
1108 return true;
1109 }
1110 return false;
1111}
1112
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1113/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1114/// sequence of memory operands that is recognized by PrologEpilogInserter.
1115MachineBasicBlock*
1116TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
1117 MachineBasicBlock *MBB) const {
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1118 MachineFunction &MF = *MI->getParent()->getParent();
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1119 MachineFrameInfo &MFI = *MF.getFrameInfo();
1120
1121 // We're handling multiple types of operands here:
1122 // PATCHPOINT MetaArgs - live-in, read only, direct
1123 // STATEPOINT Deopt Spill - live-through, read only, indirect
1124 // STATEPOINT Deopt Alloca - live-through, read only, direct
1125 // (We're currently conservative and mark the deopt slots read/write in
1126 // practice.)
1127 // STATEPOINT GC Spill - live-through, read/write, indirect
1128 // STATEPOINT GC Alloca - live-through, read/write, direct
1129 // The live-in vs live-through is handled already (the live through ones are
1130 // all stack slots), but we need to handle the different type of stackmap
1131 // operands and memory effects here.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1132
1133 // MI changes inside this loop as we grow operands.
1134 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1135 MachineOperand &MO = MI->getOperand(OperIdx);
1136 if (!MO.isFI())
1137 continue;
1138
1139 // foldMemoryOperand builds a new MI after replacing a single FI operand
1140 // with the canonical set of five x86 addressing-mode operands.
1141 int FI = MO.getIndex();
1142 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1143
1144 // Copy operands before the frame-index.
1145 for (unsigned i = 0; i < OperIdx; ++i)
1146 MIB.addOperand(MI->getOperand(i));
Philip Reamescb0f9472015-12-23 23:44:28 +0000[diff] [blame]1147 // Add frame index operands recognized by stackmaps.cpp
1148 if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1149 // indirect-mem-ref tag, size, #FI, offset.
1150 // Used for spills inserted by StatepointLowering. This codepath is not
1151 // used for patchpoints/stackmaps at all, for these spilling is done via
1152 // foldMemoryOperand callback only.
1153 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1154 MIB.addImm(StackMaps::IndirectMemRefOp);
1155 MIB.addImm(MFI.getObjectSize(FI));
1156 MIB.addOperand(MI->getOperand(OperIdx));
1157 MIB.addImm(0);
1158 } else {
1159 // direct-mem-ref tag, #FI, offset.
1160 // Used by patchpoint, and direct alloca arguments to statepoints
1161 MIB.addImm(StackMaps::DirectMemRefOp);
1162 MIB.addOperand(MI->getOperand(OperIdx));
1163 MIB.addImm(0);
1164 }
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1165 // Copy the operands after the frame index.
1166 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1167 MIB.addOperand(MI->getOperand(i));
1168
1169 // Inherit previous memory operands.
1170 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1171 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1172
1173 // Add a new memory operand for this FI.
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1174 assert(MFI.getObjectOffset(FI) != -1);
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1175
1176 unsigned Flags = MachineMemOperand::MOLoad;
1177 if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1178 Flags |= MachineMemOperand::MOStore;
1179 Flags |= MachineMemOperand::MOVolatile;
1180 }
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]1181 MachineMemOperand *MMO = MF.getMachineMemOperand(
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]1182 MachinePointerInfo::getFixedStack(MF, FI), Flags,
Mehdi Aminibd7287e2015-07-16 06:11:10 +0000[diff] [blame]1183 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1184 MIB->addMemOperand(MF, MMO);
1185
1186 // Replace the instruction and update the operand index.
1187 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1188 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1189 MI->eraseFromParent();
1190 MI = MIB;
1191 }
1192 return MBB;
1193}
1194
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1195/// findRepresentativeClass - Return the largest legal super-reg register class
1196/// of the register class for the specified type and its associated "cost".
Eric Christopher720ab842015-03-03 19:47:14 +0000[diff] [blame]1197// This function is in TargetLowering because it uses RegClassForVT which would
1198// need to be moved to TargetRegisterInfo and would necessitate moving
1199// isTypeLegal over as well - a massive change that would just require
1200// TargetLowering having a TargetRegisterInfo class member that it would use.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1201std::pair<const TargetRegisterClass *, uint8_t>
1202TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1203 MVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1204 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1205 if (!RC)
1206 return std::make_pair(RC, 0);
1207
1208 // Compute the set of all super-register classes.
1209 BitVector SuperRegRC(TRI->getNumRegClasses());
1210 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1211 SuperRegRC.setBitsInMask(RCI.getMask());
1212
1213 // Find the first legal register class with the largest spill size.
1214 const TargetRegisterClass *BestRC = RC;
1215 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1216 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1217 // We want the largest possible spill size.
1218 if (SuperRC->getSize() <= BestRC->getSize())
1219 continue;
1220 if (!isLegalRC(SuperRC))
1221 continue;
1222 BestRC = SuperRC;
1223 }
1224 return std::make_pair(BestRC, 1);
1225}
1226
1227/// computeRegisterProperties - Once all of the register classes are added,
1228/// this allows us to compute derived properties we expose.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1229void TargetLoweringBase::computeRegisterProperties(
1230 const TargetRegisterInfo *TRI) {
Craig Topper6438fc32014-11-17 00:26:50 +0000[diff] [blame]1231 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1232 "Too many value types for ValueTypeActions to hold!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1233
1234 // Everything defaults to needing one register.
1235 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1236 NumRegistersForVT[i] = 1;
1237 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1238 }
1239 // ...except isVoid, which doesn't need any registers.
1240 NumRegistersForVT[MVT::isVoid] = 0;
1241
1242 // Find the largest integer register class.
1243 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1244 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1245 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1246
1247 // Every integer value type larger than this largest register takes twice as
1248 // many registers to represent as the previous ValueType.
1249 for (unsigned ExpandedReg = LargestIntReg + 1;
1250 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1251 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1252 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1253 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1254 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1255 TypeExpandInteger);
1256 }
1257
1258 // Inspect all of the ValueType's smaller than the largest integer
1259 // register to see which ones need promotion.
1260 unsigned LegalIntReg = LargestIntReg;
1261 for (unsigned IntReg = LargestIntReg - 1;
1262 IntReg >= (unsigned)MVT::i1; --IntReg) {
1263 MVT IVT = (MVT::SimpleValueType)IntReg;
1264 if (isTypeLegal(IVT)) {
1265 LegalIntReg = IntReg;
1266 } else {
1267 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1268 (const MVT::SimpleValueType)LegalIntReg;
1269 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1270 }
1271 }
1272
1273 // ppcf128 type is really two f64's.
1274 if (!isTypeLegal(MVT::ppcf128)) {
Petar Jovanovic23e44f52016-02-04 14:43:50 +0000[diff] [blame]1275 if (isTypeLegal(MVT::f64)) {
1276 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1277 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1278 TransformToType[MVT::ppcf128] = MVT::f64;
1279 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1280 } else {
1281 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1282 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1283 TransformToType[MVT::ppcf128] = MVT::i128;
1284 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1285 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1286 }
1287
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1288 // Decide how to handle f128. If the target does not have native f128 support,
1289 // expand it to i128 and we will be generating soft float library calls.
1290 if (!isTypeLegal(MVT::f128)) {
1291 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1292 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1293 TransformToType[MVT::f128] = MVT::i128;
1294 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1295 }
1296
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1297 // Decide how to handle f64. If the target does not have native f64 support,
1298 // expand it to i64 and we will be generating soft float library calls.
1299 if (!isTypeLegal(MVT::f64)) {
1300 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1301 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1302 TransformToType[MVT::f64] = MVT::i64;
1303 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1304 }
1305
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1306 // Decide how to handle f32. If the target does not have native f32 support,
1307 // expand it to i32 and we will be generating soft float library calls.
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1308 if (!isTypeLegal(MVT::f32)) {
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1309 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1310 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1311 TransformToType[MVT::f32] = MVT::i32;
1312 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1313 }
1314
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1315 // Decide how to handle f16. If the target does not have native f16 support,
1316 // promote it to f32, because there are no f16 library calls (except for
1317 // conversions).
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1318 if (!isTypeLegal(MVT::f16)) {
Oliver Stannard56358572015-11-09 11:03:18 +0000[diff] [blame]1319 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1320 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1321 TransformToType[MVT::f16] = MVT::f32;
1322 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1323 }
1324
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1325 // Loop over all of the vector value types to see which need transformations.
1326 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1327 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1328 MVT VT = (MVT::SimpleValueType) i;
1329 if (isTypeLegal(VT))
1330 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1331
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1332 MVT EltVT = VT.getVectorElementType();
1333 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1334 bool IsLegalWiderType = false;
1335 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1336 switch (PreferredAction) {
1337 case TypePromoteInteger: {
1338 // Try to promote the elements of integer vectors. If no legal
1339 // promotion was found, fall through to the widen-vector method.
1340 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1341 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1342 // Promote vectors of integers to vectors with the same number
1343 // of elements, with a wider element type.
1344 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1345 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1346 && SVT.getScalarType().isInteger()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1347 TransformToType[i] = SVT;
1348 RegisterTypeForVT[i] = SVT;
1349 NumRegistersForVT[i] = 1;
1350 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1351 IsLegalWiderType = true;
1352 break;
1353 }
1354 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1355 if (IsLegalWiderType)
1356 break;
1357 }
1358 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1359 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1360 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1361 MVT SVT = (MVT::SimpleValueType) nVT;
1362 if (SVT.getVectorElementType() == EltVT
1363 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1364 TransformToType[i] = SVT;
1365 RegisterTypeForVT[i] = SVT;
1366 NumRegistersForVT[i] = 1;
1367 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1368 IsLegalWiderType = true;
1369 break;
1370 }
1371 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1372 if (IsLegalWiderType)
1373 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1374 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1375 case TypeSplitVector:
1376 case TypeScalarizeVector: {
1377 MVT IntermediateVT;
1378 MVT RegisterVT;
1379 unsigned NumIntermediates;
1380 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1381 NumIntermediates, RegisterVT, this);
1382 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1383
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1384 MVT NVT = VT.getPow2VectorType();
1385 if (NVT == VT) {
1386 // Type is already a power of 2. The default action is to split.
1387 TransformToType[i] = MVT::Other;
1388 if (PreferredAction == TypeScalarizeVector)
1389 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1390 else if (PreferredAction == TypeSplitVector)
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1391 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1392 else
1393 // Set type action according to the number of elements.
1394 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1395 : TypeSplitVector);
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1396 } else {
1397 TransformToType[i] = NVT;
1398 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1399 }
1400 break;
1401 }
1402 default:
1403 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1404 }
1405 }
1406
1407 // Determine the 'representative' register class for each value type.
1408 // An representative register class is the largest (meaning one which is
1409 // not a sub-register class / subreg register class) legal register class for
1410 // a group of value types. For example, on i386, i8, i16, and i32
1411 // representative would be GR32; while on x86_64 it's GR64.
1412 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1413 const TargetRegisterClass* RRC;
1414 uint8_t Cost;
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1415 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1416 RepRegClassForVT[i] = RRC;
1417 RepRegClassCostForVT[i] = Cost;
1418 }
1419}
1420
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1421EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1422 EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1423 assert(!VT.isVector() && "No default SetCC type for vectors!");
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1424 return getPointerTy(DL).SimpleTy;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1425}
1426
1427MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1428 return MVT::i32; // return the default value
1429}
1430
1431/// getVectorTypeBreakdown - Vector types are broken down into some number of
1432/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1433/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1434/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1435///
1436/// This method returns the number of registers needed, and the VT for each
1437/// register. It also returns the VT and quantity of the intermediate values
1438/// before they are promoted/expanded.
1439///
1440unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1441 EVT &IntermediateVT,
1442 unsigned &NumIntermediates,
1443 MVT &RegisterVT) const {
1444 unsigned NumElts = VT.getVectorNumElements();
1445
1446 // If there is a wider vector type with the same element type as this one,
1447 // or a promoted vector type that has the same number of elements which
1448 // are wider, then we should convert to that legal vector type.
1449 // This handles things like <2 x float> -> <4 x float> and
1450 // <4 x i1> -> <4 x i32>.
1451 LegalizeTypeAction TA = getTypeAction(Context, VT);
1452 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1453 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1454 if (isTypeLegal(RegisterEVT)) {
1455 IntermediateVT = RegisterEVT;
1456 RegisterVT = RegisterEVT.getSimpleVT();
1457 NumIntermediates = 1;
1458 return 1;
1459 }
1460 }
1461
1462 // Figure out the right, legal destination reg to copy into.
1463 EVT EltTy = VT.getVectorElementType();
1464
1465 unsigned NumVectorRegs = 1;
1466
1467 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1468 // could break down into LHS/RHS like LegalizeDAG does.
1469 if (!isPowerOf2_32(NumElts)) {
1470 NumVectorRegs = NumElts;
1471 NumElts = 1;
1472 }
1473
1474 // Divide the input until we get to a supported size. This will always
1475 // end with a scalar if the target doesn't support vectors.
1476 while (NumElts > 1 && !isTypeLegal(
1477 EVT::getVectorVT(Context, EltTy, NumElts))) {
1478 NumElts >>= 1;
1479 NumVectorRegs <<= 1;
1480 }
1481
1482 NumIntermediates = NumVectorRegs;
1483
1484 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1485 if (!isTypeLegal(NewVT))
1486 NewVT = EltTy;
1487 IntermediateVT = NewVT;
1488
1489 MVT DestVT = getRegisterType(Context, NewVT);
1490 RegisterVT = DestVT;
1491 unsigned NewVTSize = NewVT.getSizeInBits();
1492
1493 // Convert sizes such as i33 to i64.
1494 if (!isPowerOf2_32(NewVTSize))
1495 NewVTSize = NextPowerOf2(NewVTSize);
1496
1497 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1498 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1499
1500 // Otherwise, promotion or legal types use the same number of registers as
1501 // the vector decimated to the appropriate level.
1502 return NumVectorRegs;
1503}
1504
1505/// Get the EVTs and ArgFlags collections that represent the legalized return
1506/// type of the given function. This does not require a DAG or a return value,
1507/// and is suitable for use before any DAGs for the function are constructed.
1508/// TODO: Move this out of TargetLowering.cpp.
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1509void llvm::GetReturnInfo(Type *ReturnType, AttributeSet attr,
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1510 SmallVectorImpl<ISD::OutputArg> &Outs,
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1511 const TargetLowering &TLI, const DataLayout &DL) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1512 SmallVector<EVT, 4> ValueVTs;
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame]1513 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1514 unsigned NumValues = ValueVTs.size();
1515 if (NumValues == 0) return;
1516
1517 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1518 EVT VT = ValueVTs[j];
1519 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1520
1521 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1522 ExtendKind = ISD::SIGN_EXTEND;
1523 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1524 ExtendKind = ISD::ZERO_EXTEND;
1525
1526 // FIXME: C calling convention requires the return type to be promoted to
1527 // at least 32-bit. But this is not necessary for non-C calling
1528 // conventions. The frontend should mark functions whose return values
1529 // require promoting with signext or zeroext attributes.
1530 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1531 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1532 if (VT.bitsLT(MinVT))
1533 VT = MinVT;
1534 }
1535
1536 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1537 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1538
1539 // 'inreg' on function refers to return value
1540 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1541 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1542 Flags.setInReg();
1543
1544 // Propagate extension type if any
1545 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1546 Flags.setSExt();
1547 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1548 Flags.setZExt();
1549
1550 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1551 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1552 }
1553}
1554
1555/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1556/// function arguments in the caller parameter area. This is the actual
1557/// alignment, not its logarithm.
Mehdi Amini5c183d52015-07-09 02:09:28 +0000[diff] [blame]1558unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1559 const DataLayout &DL) const {
1560 return DL.getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1561}
1562
Sanjay Patel0f9dcf82015-07-29 18:24:18 +0000[diff] [blame]1563bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1564 const DataLayout &DL, EVT VT,
1565 unsigned AddrSpace,
1566 unsigned Alignment,
1567 bool *Fast) const {
1568 // Check if the specified alignment is sufficient based on the data layout.
1569 // TODO: While using the data layout works in practice, a better solution
1570 // would be to implement this check directly (make this a virtual function).
1571 // For example, the ABI alignment may change based on software platform while
1572 // this function should only be affected by hardware implementation.
1573 Type *Ty = VT.getTypeForEVT(Context);
1574 if (Alignment >= DL.getABITypeAlignment(Ty)) {
1575 // Assume that an access that meets the ABI-specified alignment is fast.
1576 if (Fast != nullptr)
1577 *Fast = true;
1578 return true;
1579 }
1580
1581 // This is a misaligned access.
1582 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1583}
1584
1585
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1586//===----------------------------------------------------------------------===//
1587// TargetTransformInfo Helpers
1588//===----------------------------------------------------------------------===//
1589
1590int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1591 enum InstructionOpcodes {
1592#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1593#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1594#include "llvm/IR/Instruction.def"
1595 };
1596 switch (static_cast<InstructionOpcodes>(Opcode)) {
1597 case Ret: return 0;
1598 case Br: return 0;
1599 case Switch: return 0;
1600 case IndirectBr: return 0;
1601 case Invoke: return 0;
1602 case Resume: return 0;
1603 case Unreachable: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1604 case CleanupRet: return 0;
David Majnemer654e1302015-07-31 17:58:14 +0000[diff] [blame]1605 case CatchRet: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1606 case CatchPad: return 0;
1607 case CatchSwitch: return 0;
David Majnemer8a1c45d2015-12-12 05:38:55 +0000[diff] [blame]1608 case CleanupPad: return 0;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1609 case Add: return ISD::ADD;
1610 case FAdd: return ISD::FADD;
1611 case Sub: return ISD::SUB;
1612 case FSub: return ISD::FSUB;
1613 case Mul: return ISD::MUL;
1614 case FMul: return ISD::FMUL;
1615 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1616 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1617 case FDiv: return ISD::FDIV;
1618 case URem: return ISD::UREM;
1619 case SRem: return ISD::SREM;
1620 case FRem: return ISD::FREM;
1621 case Shl: return ISD::SHL;
1622 case LShr: return ISD::SRL;
1623 case AShr: return ISD::SRA;
1624 case And: return ISD::AND;
1625 case Or: return ISD::OR;
1626 case Xor: return ISD::XOR;
1627 case Alloca: return 0;
1628 case Load: return ISD::LOAD;
1629 case Store: return ISD::STORE;
1630 case GetElementPtr: return 0;
1631 case Fence: return 0;
1632 case AtomicCmpXchg: return 0;
1633 case AtomicRMW: return 0;
1634 case Trunc: return ISD::TRUNCATE;
1635 case ZExt: return ISD::ZERO_EXTEND;
1636 case SExt: return ISD::SIGN_EXTEND;
1637 case FPToUI: return ISD::FP_TO_UINT;
1638 case FPToSI: return ISD::FP_TO_SINT;
1639 case UIToFP: return ISD::UINT_TO_FP;
1640 case SIToFP: return ISD::SINT_TO_FP;
1641 case FPTrunc: return ISD::FP_ROUND;
1642 case FPExt: return ISD::FP_EXTEND;
1643 case PtrToInt: return ISD::BITCAST;
1644 case IntToPtr: return ISD::BITCAST;
1645 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1646 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1647 case ICmp: return ISD::SETCC;
1648 case FCmp: return ISD::SETCC;
1649 case PHI: return 0;
1650 case Call: return 0;
1651 case Select: return ISD::SELECT;
1652 case UserOp1: return 0;
1653 case UserOp2: return 0;
1654 case VAArg: return 0;
1655 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1656 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1657 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1658 case ExtractValue: return ISD::MERGE_VALUES;
1659 case InsertValue: return ISD::MERGE_VALUES;
1660 case LandingPad: return 0;
1661 }
1662
1663 llvm_unreachable("Unknown instruction type encountered!");
1664}
1665
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1666std::pair<int, MVT>
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1667TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1668 Type *Ty) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1669 LLVMContext &C = Ty->getContext();
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]1670 EVT MTy = getValueType(DL, Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1671
Chandler Carruth93205eb2015-08-05 18:08:10 +0000[diff] [blame]1672 int Cost = 1;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1673 // We keep legalizing the type until we find a legal kind. We assume that
1674 // the only operation that costs anything is the split. After splitting
1675 // we need to handle two types.
1676 while (true) {
1677 LegalizeKind LK = getTypeConversion(C, MTy);
1678
1679 if (LK.first == TypeLegal)
1680 return std::make_pair(Cost, MTy.getSimpleVT());
1681
1682 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1683 Cost *= 2;
1684
Chih-Hung Hsiehed7d81e2015-12-03 22:02:40 +0000[diff] [blame]1685 // Do not loop with f128 type.
1686 if (MTy == LK.second)
1687 return std::make_pair(Cost, MTy.getSimpleVT());
1688
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1689 // Keep legalizing the type.
1690 MTy = LK.second;
1691 }
1692}
1693
Evgeniy Stepanovd1aad262015-10-26 18:28:25 +0000[diff] [blame]1694Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1695 if (!TM.getTargetTriple().isAndroid())
1696 return nullptr;
1697
1698 // Android provides a libc function to retrieve the address of the current
1699 // thread's unsafe stack pointer.
1700 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1701 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1702 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address",
1703 StackPtrTy->getPointerTo(0), nullptr);
1704 return IRB.CreateCall(Fn);
1705}
1706
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1707//===----------------------------------------------------------------------===//
1708// Loop Strength Reduction hooks
1709//===----------------------------------------------------------------------===//
1710
1711/// isLegalAddressingMode - Return true if the addressing mode represented
1712/// by AM is legal for this target, for a load/store of the specified type.
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000[diff] [blame]1713bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1714 const AddrMode &AM, Type *Ty,
Matt Arsenaultbd7d80a2015-06-01 05:31:59 +0000[diff] [blame]1715 unsigned AS) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1716 // The default implementation of this implements a conservative RISCy, r+r and
1717 // r+i addr mode.
1718
1719 // Allows a sign-extended 16-bit immediate field.
1720 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1721 return false;
1722
1723 // No global is ever allowed as a base.
1724 if (AM.BaseGV)
1725 return false;
1726
1727 // Only support r+r,
1728 switch (AM.Scale) {
1729 case 0: // "r+i" or just "i", depending on HasBaseReg.
1730 break;
1731 case 1:
1732 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1733 return false;
1734 // Otherwise we have r+r or r+i.
1735 break;
1736 case 2:
1737 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1738 return false;
1739 // Allow 2*r as r+r.
1740 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1741 default: // Don't allow n * r
1742 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1743 }
1744
1745 return true;
1746}