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Jia Liu9f610112012-02-17 08:55:11 +00001//===-- MipsAnalyzeImmediate.cpp - Analyze Immediates ---------------------===//
Akira Hatanakaff36fd32012-01-25 01:43:36 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9#include "MipsAnalyzeImmediate.h"
10#include "Mips.h"
11#include "llvm/Support/MathExtras.h"
12
13using namespace llvm;
14
15MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {}
16
17// Add I to the instruction sequences.
18void MipsAnalyzeImmediate::AddInstr(InstSeqLs &SeqLs, const Inst &I) {
19 // Add an instruction seqeunce consisting of just I.
20 if (SeqLs.empty()) {
21 SeqLs.push_back(InstSeq(1, I));
22 return;
23 }
24
25 for (InstSeqLs::iterator Iter = SeqLs.begin(); Iter != SeqLs.end(); ++Iter)
26 Iter->push_back(I);
27}
28
Ahmed Charles16620132012-03-09 06:36:45 +000029void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize,
Akira Hatanakaff36fd32012-01-25 01:43:36 +000030 InstSeqLs &SeqLs) {
Ahmed Charles16620132012-03-09 06:36:45 +000031 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs);
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
Akira Hatanakaff36fd32012-01-25 01:43:36 +000033}
34
Ahmed Charles16620132012-03-09 06:36:45 +000035void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize,
Akira Hatanakaff36fd32012-01-25 01:43:36 +000036 InstSeqLs &SeqLs) {
Ahmed Charles16620132012-03-09 06:36:45 +000037 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs);
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
Akira Hatanakaff36fd32012-01-25 01:43:36 +000039}
40
Ahmed Charles16620132012-03-09 06:36:45 +000041void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize,
Akira Hatanakaff36fd32012-01-25 01:43:36 +000042 InstSeqLs &SeqLs) {
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +000043 unsigned Shamt = countTrailingZeros(Imm);
Akira Hatanakaff36fd32012-01-25 01:43:36 +000044 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
45 AddInstr(SeqLs, Inst(SLL, Shamt));
46}
47
Ahmed Charles16620132012-03-09 06:36:45 +000048void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize,
Akira Hatanakaff36fd32012-01-25 01:43:36 +000049 InstSeqLs &SeqLs) {
Ahmed Charles16620132012-03-09 06:36:45 +000050 uint64_t MaskedImm = Imm & (0xffffffffffffffffULL >> (64 - Size));
Akira Hatanakaff36fd32012-01-25 01:43:36 +000051
52 // Do nothing if Imm is 0.
53 if (!MaskedImm)
54 return;
55
56 // A single ADDiu will do if RemSize <= 16.
57 if (RemSize <= 16) {
58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
59 return;
60 }
61
62 // Shift if the lower 16-bit is cleared.
63 if (!(Imm & 0xffff)) {
64 GetInstSeqLsSLL(Imm, RemSize, SeqLs);
65 return;
66 }
67
68 GetInstSeqLsADDiu(Imm, RemSize, SeqLs);
69
70 // If bit 15 is cleared, it doesn't make a difference whether the last
71 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi.
72 if (Imm & 0x8000) {
73 InstSeqLs SeqLsORi;
74 GetInstSeqLsORi(Imm, RemSize, SeqLsORi);
Benjamin Kramerc6cc58e2014-10-04 16:55:56 +000075 SeqLs.append(std::make_move_iterator(SeqLsORi.begin()),
76 std::make_move_iterator(SeqLsORi.end()));
Akira Hatanakaff36fd32012-01-25 01:43:36 +000077 }
78}
79
80// Replace a ADDiu & SLL pair with a LUi.
Jia Liuf54f60f2012-02-28 07:46:26 +000081// e.g. the following two instructions
Akira Hatanakaff36fd32012-01-25 01:43:36 +000082// ADDiu 0x0111
83// SLL 18
84// are replaced with
85// LUi 0x444
86void MipsAnalyzeImmediate::ReplaceADDiuSLLWithLUi(InstSeq &Seq) {
87 // Check if the first two instructions are ADDiu and SLL and the shift amount
88 // is at least 16.
89 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
90 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16))
91 return;
92
93 // Sign-extend and shift operand of ADDiu and see if it still fits in 16-bit.
Akira Hatanakaa7721f62012-02-22 00:16:54 +000094 int64_t Imm = SignExtend64<16>(Seq[0].ImmOpnd);
Richard Smith228e6d42012-08-24 23:29:28 +000095 int64_t ShiftedImm = (uint64_t)Imm << (Seq[1].ImmOpnd - 16);
Akira Hatanakaff36fd32012-01-25 01:43:36 +000096
97 if (!isInt<16>(ShiftedImm))
98 return;
99
100 // Replace the first instruction and erase the second.
101 Seq[0].Opc = LUi;
102 Seq[0].ImmOpnd = (unsigned)(ShiftedImm & 0xffff);
103 Seq.erase(Seq.begin() + 1);
104}
105
106void MipsAnalyzeImmediate::GetShortestSeq(InstSeqLs &SeqLs, InstSeq &Insts) {
107 InstSeqLs::iterator ShortestSeq = SeqLs.end();
108 // The length of an instruction sequence is at most 7.
109 unsigned ShortestLength = 8;
110
111 for (InstSeqLs::iterator S = SeqLs.begin(); S != SeqLs.end(); ++S) {
112 ReplaceADDiuSLLWithLUi(*S);
113 assert(S->size() <= 7);
114
115 if (S->size() < ShortestLength) {
116 ShortestSeq = S;
117 ShortestLength = S->size();
118 }
119 }
120
121 Insts.clear();
122 Insts.append(ShortestSeq->begin(), ShortestSeq->end());
123}
124
125const MipsAnalyzeImmediate::InstSeq
Ahmed Charles16620132012-03-09 06:36:45 +0000126&MipsAnalyzeImmediate::Analyze(uint64_t Imm, unsigned Size,
Akira Hatanakaff36fd32012-01-25 01:43:36 +0000127 bool LastInstrIsADDiu) {
128 this->Size = Size;
129
130 if (Size == 32) {
131 ADDiu = Mips::ADDiu;
132 ORi = Mips::ORi;
133 SLL = Mips::SLL;
134 LUi = Mips::LUi;
135 } else {
136 ADDiu = Mips::DADDiu;
137 ORi = Mips::ORi64;
138 SLL = Mips::DSLL;
139 LUi = Mips::LUi64;
140 }
141
142 InstSeqLs SeqLs;
143
144 // Get the list of instruction sequences.
145 if (LastInstrIsADDiu | !Imm)
146 GetInstSeqLsADDiu(Imm, Size, SeqLs);
147 else
148 GetInstSeqLs(Imm, Size, SeqLs);
149
150 // Set Insts to the shortest instruction sequence.
151 GetShortestSeq(SeqLs, Insts);
152
Jia Liuf54f60f2012-02-28 07:46:26 +0000153 return Insts;
Akira Hatanakaff36fd32012-01-25 01:43:36 +0000154}