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gerrit-public.fairphone.software / toolchain / llvm-project / 91e2b9d081829af95a7b84ec5393e33539e9130e / . / llvm / test / CodeGen / X86 / combine-smin.ll
blob: 428879a51e079d7cf4400b287d5c5ac055b055e3 [file] [log] [blame]
Simon Pilgrimd229bfd2018-02-10 23:38:50 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE42
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
9
10define <16 x i8> @test_v16i8_nosignbit(<16 x i8> %a, <16 x i8> %b) {
11; SSE2-LABEL: test_v16i8_nosignbit:
12; SSE2: # %bb.0:
13; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
14; SSE2-NEXT: pand %xmm2, %xmm0
15; SSE2-NEXT: pand %xmm2, %xmm1
16; SSE2-NEXT: movdqa %xmm1, %xmm2
17; SSE2-NEXT: pcmpgtb %xmm0, %xmm2
18; SSE2-NEXT: pand %xmm2, %xmm0
19; SSE2-NEXT: pandn %xmm1, %xmm2
20; SSE2-NEXT: por %xmm2, %xmm0
21; SSE2-NEXT: retq
22;
23; SSE41-LABEL: test_v16i8_nosignbit:
24; SSE41: # %bb.0:
25; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
26; SSE41-NEXT: pand %xmm2, %xmm0
27; SSE41-NEXT: pand %xmm2, %xmm1
28; SSE41-NEXT: pminsb %xmm1, %xmm0
29; SSE41-NEXT: retq
30;
31; SSE42-LABEL: test_v16i8_nosignbit:
32; SSE42: # %bb.0:
33; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
34; SSE42-NEXT: pand %xmm2, %xmm0
35; SSE42-NEXT: pand %xmm2, %xmm1
36; SSE42-NEXT: pminsb %xmm1, %xmm0
37; SSE42-NEXT: retq
38;
39; AVX-LABEL: test_v16i8_nosignbit:
40; AVX: # %bb.0:
41; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
42; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0
43; AVX-NEXT: vpand %xmm2, %xmm1, %xmm1
44; AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0
45; AVX-NEXT: retq
46 %1 = and <16 x i8> %a, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
47 %2 = and <16 x i8> %b, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
48 %3 = icmp slt <16 x i8> %1, %2
49 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
50 ret <16 x i8> %4
51}