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gerrit-public.fairphone.software / toolchain / llvm-project / 4c9ed3ed3d2fc7622acf5fc0d80ad20b44cf376a / . / llvm / lib / Support / X86TargetParser.cpp
blob: 572d1203aaf21b59a7765ded3380cc8b87754649 [file] [log] [blame]
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/Support/X86TargetParser.h"
14#include "llvm/ADT/StringSwitch.h"
15#include "llvm/ADT/Triple.h"
16
17using namespace llvm;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]18using namespace llvm::X86;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]19
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]20namespace {
21
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]22/// Container class for CPU features.
23/// This is a constexpr reimplementation of a subset of std::bitset. It would be
24/// nice to use std::bitset directly, but it doesn't support constant
25/// initialization.
26class FeatureBitset {
27 static constexpr unsigned NUM_FEATURE_WORDS =
28 (X86::CPU_FEATURE_MAX + 31) / 32;
29
30 // This cannot be a std::array, operator[] is not constexpr until C++17.
31 uint32_t Bits[NUM_FEATURE_WORDS] = {};
32
33public:
34 constexpr FeatureBitset() = default;
35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36 for (auto I : Init)
37 set(I);
38 }
39
40 constexpr FeatureBitset &set(unsigned I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]41 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]42 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
43 Bits[I / 32] = NewBits;
44 return *this;
45 }
46
47 constexpr bool operator[](unsigned I) const {
48 uint32_t Mask = uint32_t(1) << (I % 32);
49 return (Bits[I / 32] & Mask) != 0;
50 }
51
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]52 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
53 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
54 // GCC <6.2 crashes if this is written in a single statement.
55 uint32_t NewBits = Bits[I] & RHS.Bits[I];
56 Bits[I] = NewBits;
57 }
58 return *this;
59 }
60
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]61 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
62 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]63 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]64 uint32_t NewBits = Bits[I] | RHS.Bits[I];
65 Bits[I] = NewBits;
66 }
67 return *this;
68 }
69
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]70 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]71 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]72 FeatureBitset Result;
73 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
74 Result.Bits[I] = Bits[I] & RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]75 return Result;
76 }
77
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]78 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]79 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]80 FeatureBitset Result;
81 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
82 Result.Bits[I] = Bits[I] | RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]83 return Result;
84 }
85
86 constexpr FeatureBitset operator~() const {
87 FeatureBitset Result;
88 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
89 Result.Bits[I] = ~Bits[I];
90 return Result;
91 }
92};
93
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]94struct ProcInfo {
95 StringLiteral Name;
96 X86::CPUKind Kind;
97 unsigned KeyFeature;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]98 FeatureBitset Features;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]99};
100
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]101struct FeatureInfo {
102 StringLiteral Name;
103 FeatureBitset ImpliedFeatures;
104};
105
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]106} // end anonymous namespace
107
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]108#define X86_FEATURE(ENUM, STRING) \
109 static constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
110#include "llvm/Support/X86TargetParser.def"
111
112// Pentium with MMX.
113static constexpr FeatureBitset FeaturesPentiumMMX =
114 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
115
116// Pentium 2 and 3.
117static constexpr FeatureBitset FeaturesPentium2 =
118 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
119static constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
120
121// Pentium 4 CPUs
122static constexpr FeatureBitset FeaturesPentium4 =
123 FeaturesPentium3 | FeatureSSE2;
124static constexpr FeatureBitset FeaturesPrescott =
125 FeaturesPentium4 | FeatureSSE3;
126static constexpr FeatureBitset FeaturesNocona =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]127 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]128
129// Basic 64-bit capable CPU.
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]130static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]131
132// Intel Core CPUs
133static constexpr FeatureBitset FeaturesCore2 =
134 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
135static constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
136static constexpr FeatureBitset FeaturesNehalem =
137 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
138static constexpr FeatureBitset FeaturesWestmere =
139 FeaturesNehalem | FeaturePCLMUL;
140static constexpr FeatureBitset FeaturesSandyBridge =
141 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
142static constexpr FeatureBitset FeaturesIvyBridge =
143 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
144static constexpr FeatureBitset FeaturesHaswell =
145 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
146 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
147static constexpr FeatureBitset FeaturesBroadwell =
148 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
149
150// Intel Knights Landing and Knights Mill
151// Knights Landing has feature parity with Broadwell.
152static constexpr FeatureBitset FeaturesKNL =
153 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
154 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
155static constexpr FeatureBitset FeaturesKNM =
156 FeaturesKNL | FeatureAVX512VPOPCNTDQ;
157
158// Intel Skylake processors.
159static constexpr FeatureBitset FeaturesSkylakeClient =
160 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
161 FeatureXSAVES | FeatureSGX;
162// SkylakeServer inherits all SkylakeClient features except SGX.
163// FIXME: That doesn't match gcc.
164static constexpr FeatureBitset FeaturesSkylakeServer =
165 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
166 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
167 FeaturePKU;
168static constexpr FeatureBitset FeaturesCascadeLake =
169 FeaturesSkylakeServer | FeatureAVX512VNNI;
170static constexpr FeatureBitset FeaturesCooperLake =
171 FeaturesCascadeLake | FeatureAVX512BF16;
172
173// Intel 10nm processors.
174static constexpr FeatureBitset FeaturesCannonlake =
175 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
176 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
177 FeaturePKU | FeatureSHA;
178static constexpr FeatureBitset FeaturesICLClient =
179 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
180 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
181 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
182static constexpr FeatureBitset FeaturesICLServer =
183 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
184static constexpr FeatureBitset FeaturesTigerlake =
185 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
186 FeatureMOVDIRI | FeatureSHSTK;
187
188// Intel Atom processors.
189// Bonnell has feature parity with Core2 and adds MOVBE.
190static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
191// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
192static constexpr FeatureBitset FeaturesSilvermont =
193 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
194static constexpr FeatureBitset FeaturesGoldmont =
195 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
196 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
197 FeatureXSAVEOPT | FeatureXSAVES;
198static constexpr FeatureBitset FeaturesGoldmontPlus =
199 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
200static constexpr FeatureBitset FeaturesTremont =
201 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
202
203// Geode Processor.
204static constexpr FeatureBitset FeaturesGeode =
205 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
206
207// K6 processor.
208static constexpr FeatureBitset FeaturesK6 =
209 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
210
211// K7 and K8 architecture processors.
212static constexpr FeatureBitset FeaturesAthlon =
213 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
214static constexpr FeatureBitset FeaturesAthlonXP =
215 FeaturesAthlon | FeatureFXSR | FeatureSSE;
216static constexpr FeatureBitset FeaturesK8 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]217 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]218static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
219static constexpr FeatureBitset FeaturesAMDFAM10 =
220 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]221 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]222
223// Bobcat architecture processors.
224static constexpr FeatureBitset FeaturesBTVER1 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]225 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]226 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]227 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]228 FeatureSAHF;
229static constexpr FeatureBitset FeaturesBTVER2 =
230 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
231 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
232
233// AMD Bulldozer architecture processors.
234static constexpr FeatureBitset FeaturesBDVER1 =
235 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]236 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]237 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
238 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]239 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]240static constexpr FeatureBitset FeaturesBDVER2 =
241 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
242static constexpr FeatureBitset FeaturesBDVER3 =
243 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
244static constexpr FeatureBitset FeaturesBDVER4 =
245 FeaturesBDVER3 | FeatureAVX2 | FeatureBMI2 | FeatureMOVBE | FeatureMWAITX |
246 FeatureRDRND;
247
248// AMD Zen architecture processors.
249static constexpr FeatureBitset FeaturesZNVER1 =
250 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
251 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]252 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]253 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
254 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
255 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
256 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]257 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]258 FeatureXSAVEOPT | FeatureXSAVES;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]259static constexpr FeatureBitset FeaturesZNVER2 =
260 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]261
262static constexpr ProcInfo Processors[] = {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]263 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
264 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]265 // i386-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]266 { {"i386"}, CK_i386, ~0U, FeatureX87 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]267 // i486-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]268 { {"i486"}, CK_i486, ~0U, FeatureX87 },
269 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
270 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
271 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]272 // i586-generation processors, P5 microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]273 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
274 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
275 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]276 // i686-generation processors, P6 / Pentium M microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]277 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
278 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
279 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
280 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
281 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
282 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
283 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
284 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]285 // Netburst microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]286 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
287 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
288 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
289 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]290 // Core microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]291 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
292 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]293 // Atom processors
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]294 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
295 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
296 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
297 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
298 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
299 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
300 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]301 // Nehalem microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]302 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
303 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]304 // Westmere microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]305 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]306 // Sandy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]307 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
308 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]309 // Ivy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]310 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
311 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]312 // Haswell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]313 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
314 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]315 // Broadwell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]316 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]317 // Skylake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]318 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]319 // Skylake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]320 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
321 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]322 // Cascadelake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]323 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]324 // Cooperlake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]325 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]326 // Cannonlake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]327 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]328 // Icelake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]329 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]330 // Icelake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]331 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]332 // Tigerlake microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]333 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]334 // Knights Landing processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]335 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]336 // Knights Mill processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]337 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]338 // Lakemont microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]339 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]340 // K6 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]341 { {"k6"}, CK_K6, ~0U, FeaturesK6 },
342 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
343 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]344 // K7 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]345 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
346 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
347 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
348 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
349 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]350 // K8 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]351 { {"k8"}, CK_K8, ~0U, FeaturesK8 },
352 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
353 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
354 { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
355 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
356 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
357 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
358 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
359 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]360 // Bobcat architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]361 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
362 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]363 // Bulldozer architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]364 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
365 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
366 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
367 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]368 // Zen architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]369 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
370 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]371 // Generic 64-bit processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]372 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]373 // Geode processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]374 { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]375};
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]376
377X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]378 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]379 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]380 return P.Kind;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]381
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]382 return CK_None;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]383}
384
385void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
386 bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]387 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]388 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]389 Values.emplace_back(P.Name);
390}
391
392ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
393 // FIXME: Can we avoid a linear search here? The table might be sorted by
394 // CPUKind so we could binary search?
395 for (const auto &P : Processors) {
396 if (P.Kind == Kind) {
397 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
398 return static_cast<ProcessorFeatures>(P.KeyFeature);
399 }
400 }
401
402 llvm_unreachable("Unable to find CPU kind!");
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]403}
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]404
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]405// Features with no dependencies.
Craig Topper44ea81a2020-07-07 00:27:50 -0700[diff] [blame]406static constexpr FeatureBitset ImpliedFeatures64BIT = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]407static constexpr FeatureBitset ImpliedFeaturesADX = {};
408static constexpr FeatureBitset ImpliedFeaturesBMI = {};
409static constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
410static constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
411static constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
412static constexpr FeatureBitset ImpliedFeaturesCLWB = {};
413static constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
414static constexpr FeatureBitset ImpliedFeaturesCMOV = {};
415static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
416static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]417static constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
418static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
419static constexpr FeatureBitset ImpliedFeaturesFXSR = {};
420static constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
421static constexpr FeatureBitset ImpliedFeaturesLWP = {};
422static constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
423static constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
424static constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
425static constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
426static constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
427static constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
428static constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
429static constexpr FeatureBitset ImpliedFeaturesPKU = {};
430static constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
431static constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
432static constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
433static constexpr FeatureBitset ImpliedFeaturesRDPID = {};
434static constexpr FeatureBitset ImpliedFeaturesRDRND = {};
435static constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
436static constexpr FeatureBitset ImpliedFeaturesRTM = {};
437static constexpr FeatureBitset ImpliedFeaturesSAHF = {};
438static constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
439static constexpr FeatureBitset ImpliedFeaturesSGX = {};
440static constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
441static constexpr FeatureBitset ImpliedFeaturesTBM = {};
442static constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
443static constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
444static constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
445static constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
446static constexpr FeatureBitset ImpliedFeaturesX87 = {};
447static constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
448
449// Not really CPU features, but need to be in the table because clang uses
450// target features to communicate them to the backend.
Craig Topper44ea81a2020-07-07 00:27:50 -0700[diff] [blame]451static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]452static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
453static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
454static constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
455static constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
456
457// XSAVE features are dependent on basic XSAVE.
458static constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
459static constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
460static constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
461
462// MMX->3DNOW->3DNOWA chain.
463static constexpr FeatureBitset ImpliedFeaturesMMX = {};
464static constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
465static constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
466
467// SSE/AVX/AVX512F chain.
468static constexpr FeatureBitset ImpliedFeaturesSSE = {};
469static constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
470static constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
471static constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
472static constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
473static constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
474static constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
475static constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
476static constexpr FeatureBitset ImpliedFeaturesAVX512F =
477 FeatureAVX2 | FeatureF16C | FeatureFMA;
478
479// Vector extensions that build on SSE or AVX.
480static constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
481static constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
482static constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
483static constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
484static constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
485static constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
486static constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
487static constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ =
488 FeatureAVX | FeaturePCLMUL;
489
490// AVX512 features.
491static constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
492static constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
493static constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
494static constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
495static constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
496static constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
497
498static constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
499static constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
500static constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
501static constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
502static constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
503static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
504static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
505static constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT =
506 FeatureAVX512F;
507
508// FIXME: These two aren't really implemented and just exist in the feature
509// list for __builtin_cpu_supports. So omit their dependencies.
510static constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
511static constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
512
513// SSE4_A->FMA4->XOP chain.
514static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSSE3;
515static constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
516static constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
517
518// AMX Features
519static constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
520static constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
521static constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
522
523static constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
524#define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]525#include "llvm/Support/X86TargetParser.def"
526};
527
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]528// Convert the set bits in FeatureBitset to a list of strings.
529static void getFeatureBitsAsStrings(const FeatureBitset &Bits,
530 SmallVectorImpl<StringRef> &Features) {
531 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
532 if (Bits[i] && !FeatureInfos[i].Name.empty())
533 Features.push_back(FeatureInfos[i].Name);
534}
535
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]536void llvm::X86::getFeaturesForCPU(StringRef CPU,
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]537 SmallVectorImpl<StringRef> &EnabledFeatures) {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]538 auto I = llvm::find_if(Processors,
539 [&](const ProcInfo &P) { return P.Name == CPU; });
540 assert(I != std::end(Processors) && "Processor not found!");
541
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]542 FeatureBitset Bits = I->Features;
543
544 // Remove the 64-bit feature which we only use to validate if a CPU can
545 // be used with 64-bit mode.
546 Bits &= ~Feature64BIT;
547
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]548 // Add the string version of all set bits.
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]549 getFeatureBitsAsStrings(Bits, EnabledFeatures);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]550}
551
552// For each feature that is (transitively) implied by this feature, set it.
553static void getImpliedEnabledFeatures(FeatureBitset &Bits,
554 const FeatureBitset &Implies) {
555 Bits |= Implies;
556 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) {
557 if (Implies[i])
558 getImpliedEnabledFeatures(Bits, FeatureInfos[i].ImpliedFeatures);
559 }
560}
561
562/// Create bit vector of features that are implied disabled if the feature
563/// passed in Value is disabled.
564static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
565 // Check all features looking for any dependent on this feature. If we find
566 // one, mark it and recursively find any feature that depend on it.
567 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) {
568 if (FeatureInfos[i].ImpliedFeatures[Value]) {
569 Bits.set(i);
570 getImpliedDisabledFeatures(Bits, i);
571 }
572 }
573}
574
575void llvm::X86::getImpliedFeatures(
576 StringRef Feature, bool Enabled,
577 SmallVectorImpl<StringRef> &ImpliedFeatures) {
578 auto I = llvm::find_if(
579 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
580 if (I == std::end(FeatureInfos)) {
Craig Topper44ea81a2020-07-07 00:27:50 -0700[diff] [blame]581 // FIXME: This shouldn't happen, but may not have all features in the table
582 // yet.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]583 return;
584 }
585
586 FeatureBitset ImpliedBits;
587 if (Enabled)
588 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
589 else
590 getImpliedDisabledFeatures(ImpliedBits,
591 std::distance(std::begin(FeatureInfos), I));
592
593 // Convert all the found bits into strings.
594 getFeatureBitsAsStrings(ImpliedBits, ImpliedFeatures);
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]595}