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Eugene Zelenko79220eae2017-08-03 22:12:30 +00001//===- MipsSEFrameLowering.cpp - Mips32/64 Frame Information --------------===//
Akira Hatanakad1c43ce2012-07-31 22:50:19 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips32/64 implementation of TargetFrameLowering class.
11//
12//===----------------------------------------------------------------------===//
13
Chandler Carruth6bda14b2017-06-06 11:49:48 +000014#include "MipsSEFrameLowering.h"
Eugene Zelenko926883e2017-02-01 01:22:51 +000015#include "MCTargetDesc/MipsABIInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000016#include "MipsMachineFunction.h"
Eugene Zelenko926883e2017-02-01 01:22:51 +000017#include "MipsRegisterInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000018#include "MipsSEInstrInfo.h"
Eric Christopher4cdb3f92014-07-02 23:29:55 +000019#include "MipsSubtarget.h"
Eugene Zelenko926883e2017-02-01 01:22:51 +000020#include "llvm/ADT/BitVector.h"
21#include "llvm/ADT/StringRef.h"
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +000022#include "llvm/ADT/StringSwitch.h"
Eugene Zelenko926883e2017-02-01 01:22:51 +000023#include "llvm/CodeGen/MachineBasicBlock.h"
Akira Hatanakad1c43ce2012-07-31 22:50:19 +000024#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
Eugene Zelenko926883e2017-02-01 01:22:51 +000026#include "llvm/CodeGen/MachineInstr.h"
Akira Hatanakad1c43ce2012-07-31 22:50:19 +000027#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
Eugene Zelenko926883e2017-02-01 01:22:51 +000029#include "llvm/CodeGen/MachineOperand.h"
Akira Hatanakad1c43ce2012-07-31 22:50:19 +000030#include "llvm/CodeGen/MachineRegisterInfo.h"
Akira Hatanaka5852e3b2012-11-03 00:05:43 +000031#include "llvm/CodeGen/RegisterScavenging.h"
Eugene Zelenko926883e2017-02-01 01:22:51 +000032#include "llvm/IR/DebugLoc.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000033#include "llvm/IR/Function.h"
Eugene Zelenko926883e2017-02-01 01:22:51 +000034#include "llvm/MC/MCDwarf.h"
35#include "llvm/MC/MCRegisterInfo.h"
36#include "llvm/MC/MachineLocation.h"
37#include "llvm/Support/CodeGen.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/MathExtras.h"
40#include "llvm/Target/TargetInstrInfo.h"
41#include "llvm/Target/TargetRegisterInfo.h"
42#include "llvm/Target/TargetSubtargetInfo.h"
43#include <cassert>
44#include <cstdint>
45#include <utility>
46#include <vector>
Akira Hatanakad1c43ce2012-07-31 22:50:19 +000047
48using namespace llvm;
49
Akira Hatanaka16048332013-10-07 18:49:46 +000050static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) {
51 if (Mips::ACC64RegClass.contains(Src))
52 return std::make_pair((unsigned)Mips::PseudoMFHI,
53 (unsigned)Mips::PseudoMFLO);
54
55 if (Mips::ACC64DSPRegClass.contains(Src))
56 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
57
58 if (Mips::ACC128RegClass.contains(Src))
59 return std::make_pair((unsigned)Mips::PseudoMFHI64,
60 (unsigned)Mips::PseudoMFLO64);
61
62 return std::make_pair(0, 0);
63}
64
Eugene Zelenko926883e2017-02-01 01:22:51 +000065namespace {
66
Akira Hatanakaae4a5562013-05-01 23:41:31 +000067/// Helper class to expand pseudos.
68class ExpandPseudo {
Akira Hatanaka3b701452013-03-30 01:04:11 +000069public:
Akira Hatanakaae4a5562013-05-01 23:41:31 +000070 ExpandPseudo(MachineFunction &MF);
Akira Hatanaka3b701452013-03-30 01:04:11 +000071 bool expand();
72
73private:
Eugene Zelenko79220eae2017-08-03 22:12:30 +000074 using Iter = MachineBasicBlock::iterator;
Eugene Zelenko926883e2017-02-01 01:22:51 +000075
Akira Hatanaka3b701452013-03-30 01:04:11 +000076 bool expandInstr(MachineBasicBlock &MBB, Iter I);
Akira Hatanaka5705f542013-05-02 23:07:05 +000077 void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
78 void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
Akira Hatanakaae4a5562013-05-01 23:41:31 +000079 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
Akira Hatanaka16048332013-10-07 18:49:46 +000080 void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
81 unsigned MFLoOpc, unsigned RegSize);
Akira Hatanaka42543192013-04-30 23:22:09 +000082 bool expandCopy(MachineBasicBlock &MBB, Iter I);
Akira Hatanaka16048332013-10-07 18:49:46 +000083 bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
84 unsigned MFLoOpc);
Sasa Stankovicb976fee2014-07-14 09:40:29 +000085 bool expandBuildPairF64(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator I, bool FP64) const;
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +000087 bool expandExtractElementF64(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator I, bool FP64) const;
Akira Hatanaka3b701452013-03-30 01:04:11 +000089
90 MachineFunction &MF;
Akira Hatanaka3b701452013-03-30 01:04:11 +000091 MachineRegisterInfo &MRI;
Eric Christopher96e72c62015-01-29 23:27:36 +000092 const MipsSubtarget &Subtarget;
93 const MipsSEInstrInfo &TII;
94 const MipsRegisterInfo &RegInfo;
Akira Hatanaka3b701452013-03-30 01:04:11 +000095};
Eugene Zelenko926883e2017-02-01 01:22:51 +000096
97} // end anonymous namespace
Akira Hatanaka3b701452013-03-30 01:04:11 +000098
Akira Hatanakaae4a5562013-05-01 23:41:31 +000099ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
Eric Christopher96e72c62015-01-29 23:27:36 +0000100 : MF(MF_), MRI(MF.getRegInfo()),
101 Subtarget(static_cast<const MipsSubtarget &>(MF.getSubtarget())),
102 TII(*static_cast<const MipsSEInstrInfo *>(Subtarget.getInstrInfo())),
103 RegInfo(*Subtarget.getRegisterInfo()) {}
Akira Hatanaka3b701452013-03-30 01:04:11 +0000104
Akira Hatanakaae4a5562013-05-01 23:41:31 +0000105bool ExpandPseudo::expand() {
Akira Hatanaka3b701452013-03-30 01:04:11 +0000106 bool Expanded = false;
107
Vasileios Kalintiris5a971a42016-04-15 20:43:17 +0000108 for (auto &MBB : MF) {
109 for (Iter I = MBB.begin(), End = MBB.end(); I != End;)
110 Expanded |= expandInstr(MBB, I++);
111 }
Akira Hatanaka3b701452013-03-30 01:04:11 +0000112
113 return Expanded;
114}
115
Akira Hatanakaae4a5562013-05-01 23:41:31 +0000116bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
Akira Hatanaka3b701452013-03-30 01:04:11 +0000117 switch(I->getOpcode()) {
Akira Hatanaka5705f542013-05-02 23:07:05 +0000118 case Mips::LOAD_CCOND_DSP:
Akira Hatanaka5705f542013-05-02 23:07:05 +0000119 expandLoadCCond(MBB, I);
120 break;
121 case Mips::STORE_CCOND_DSP:
Akira Hatanaka5705f542013-05-02 23:07:05 +0000122 expandStoreCCond(MBB, I);
123 break;
Akira Hatanaka00fcf2e2013-08-08 21:54:26 +0000124 case Mips::LOAD_ACC64:
Akira Hatanaka00fcf2e2013-08-08 21:54:26 +0000125 case Mips::LOAD_ACC64DSP:
Akira Hatanakaae4a5562013-05-01 23:41:31 +0000126 expandLoadACC(MBB, I, 4);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000127 break;
Akira Hatanaka00fcf2e2013-08-08 21:54:26 +0000128 case Mips::LOAD_ACC128:
Akira Hatanakaae4a5562013-05-01 23:41:31 +0000129 expandLoadACC(MBB, I, 8);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000130 break;
Akira Hatanaka00fcf2e2013-08-08 21:54:26 +0000131 case Mips::STORE_ACC64:
Akira Hatanaka16048332013-10-07 18:49:46 +0000132 expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
133 break;
Akira Hatanaka00fcf2e2013-08-08 21:54:26 +0000134 case Mips::STORE_ACC64DSP:
Akira Hatanaka16048332013-10-07 18:49:46 +0000135 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000136 break;
Akira Hatanaka00fcf2e2013-08-08 21:54:26 +0000137 case Mips::STORE_ACC128:
Akira Hatanaka16048332013-10-07 18:49:46 +0000138 expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000139 break;
Sasa Stankovicb976fee2014-07-14 09:40:29 +0000140 case Mips::BuildPairF64:
141 if (expandBuildPairF64(MBB, I, false))
142 MBB.erase(I);
143 return false;
144 case Mips::BuildPairF64_64:
145 if (expandBuildPairF64(MBB, I, true))
146 MBB.erase(I);
147 return false;
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000148 case Mips::ExtractElementF64:
149 if (expandExtractElementF64(MBB, I, false))
150 MBB.erase(I);
151 return false;
152 case Mips::ExtractElementF64_64:
153 if (expandExtractElementF64(MBB, I, true))
154 MBB.erase(I);
155 return false;
Akira Hatanaka42543192013-04-30 23:22:09 +0000156 case TargetOpcode::COPY:
157 if (!expandCopy(MBB, I))
158 return false;
Akira Hatanaka3b701452013-03-30 01:04:11 +0000159 break;
160 default:
161 return false;
162 }
163
164 MBB.erase(I);
165 return true;
166}
167
Akira Hatanaka5705f542013-05-02 23:07:05 +0000168void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
169 // load $vr, FI
170 // copy ccond, $vr
171
172 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
173
174 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
175 unsigned VR = MRI.createVirtualRegister(RC);
176 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
177
178 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
179 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
180 .addReg(VR, RegState::Kill);
181}
182
183void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
184 // copy $vr, ccond
185 // store $vr, FI
186
187 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
188
189 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
190 unsigned VR = MRI.createVirtualRegister(RC);
191 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
192
193 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
194 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
195 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
196}
197
Akira Hatanakaae4a5562013-05-01 23:41:31 +0000198void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
Akira Hatanaka3b701452013-03-30 01:04:11 +0000199 unsigned RegSize) {
200 // load $vr0, FI
201 // copy lo, $vr0
202 // load $vr1, FI + 4
203 // copy hi, $vr1
204
205 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
206
207 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
208 unsigned VR0 = MRI.createVirtualRegister(RC);
209 unsigned VR1 = MRI.createVirtualRegister(RC);
210 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
211 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
212 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
213 DebugLoc DL = I->getDebugLoc();
214 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
215
216 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
217 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
218 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
219 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
220}
221
Akira Hatanakaae4a5562013-05-01 23:41:31 +0000222void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
Akira Hatanaka16048332013-10-07 18:49:46 +0000223 unsigned MFHiOpc, unsigned MFLoOpc,
Akira Hatanaka3b701452013-03-30 01:04:11 +0000224 unsigned RegSize) {
Akira Hatanaka16048332013-10-07 18:49:46 +0000225 // mflo $vr0, src
Akira Hatanaka3b701452013-03-30 01:04:11 +0000226 // store $vr0, FI
Akira Hatanaka16048332013-10-07 18:49:46 +0000227 // mfhi $vr1, src
Akira Hatanaka3b701452013-03-30 01:04:11 +0000228 // store $vr1, FI + 4
229
230 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
231
232 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
233 unsigned VR0 = MRI.createVirtualRegister(RC);
234 unsigned VR1 = MRI.createVirtualRegister(RC);
235 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
236 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
Akira Hatanaka3b701452013-03-30 01:04:11 +0000237 DebugLoc DL = I->getDebugLoc();
238
Akira Hatanaka16048332013-10-07 18:49:46 +0000239 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000240 TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
Akira Hatanaka16048332013-10-07 18:49:46 +0000241 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000242 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
243}
244
Akira Hatanakaae4a5562013-05-01 23:41:31 +0000245bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
Akira Hatanaka16048332013-10-07 18:49:46 +0000246 unsigned Src = I->getOperand(1).getReg();
247 std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
Akira Hatanaka42543192013-04-30 23:22:09 +0000248
Akira Hatanaka16048332013-10-07 18:49:46 +0000249 if (!Opcodes.first)
250 return false;
Akira Hatanaka42543192013-04-30 23:22:09 +0000251
Akira Hatanaka16048332013-10-07 18:49:46 +0000252 return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
Akira Hatanakaae4a5562013-05-01 23:41:31 +0000253}
254
Akira Hatanaka16048332013-10-07 18:49:46 +0000255bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
256 unsigned MFHiOpc, unsigned MFLoOpc) {
257 // mflo $vr0, src
Akira Hatanaka3b701452013-03-30 01:04:11 +0000258 // copy dst_lo, $vr0
Akira Hatanaka16048332013-10-07 18:49:46 +0000259 // mfhi $vr1, src
Akira Hatanaka3b701452013-03-30 01:04:11 +0000260 // copy dst_hi, $vr1
261
Akira Hatanaka16048332013-10-07 18:49:46 +0000262 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
Krzysztof Parzyszek44e25f32017-04-24 18:55:33 +0000263 const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst);
264 unsigned VRegSize = RegInfo.getRegSizeInBits(*DstRC) / 16;
Akira Hatanaka16048332013-10-07 18:49:46 +0000265 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000266 unsigned VR0 = MRI.createVirtualRegister(RC);
267 unsigned VR1 = MRI.createVirtualRegister(RC);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000268 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
269 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
270 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000271 DebugLoc DL = I->getDebugLoc();
272
Akira Hatanaka16048332013-10-07 18:49:46 +0000273 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000274 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
275 .addReg(VR0, RegState::Kill);
Akira Hatanaka16048332013-10-07 18:49:46 +0000276 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000277 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
278 .addReg(VR1, RegState::Kill);
Akira Hatanaka42543192013-04-30 23:22:09 +0000279 return true;
Akira Hatanaka3b701452013-03-30 01:04:11 +0000280}
281
Sasa Stankovicb976fee2014-07-14 09:40:29 +0000282/// This method expands the same instruction that MipsSEInstrInfo::
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000283/// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not
284/// available and the case where the ABI is FP64A. It is implemented here
285/// because frame indexes are eliminated before MipsSEInstrInfo::
286/// expandBuildPairF64 is called.
Sasa Stankovicb976fee2014-07-14 09:40:29 +0000287bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
288 MachineBasicBlock::iterator I,
289 bool FP64) const {
290 // For fpxx and when mthc1 is not available, use:
291 // spill + reload via ldc1
292 //
293 // The case where dmtc1 is available doesn't need to be handled here
294 // because it never creates a BuildPairF64 node.
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000295 //
296 // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
297 // for odd-numbered double precision values (because the lower 32-bits is
298 // transferred with mtc1 which is redirected to the upper half of the even
299 // register). Unfortunately, we have to make this decision before register
300 // allocation so for now we use a spill/reload sequence for all
301 // double-precision values in regardless of being an odd/even register.
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000302 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
303 (FP64 && !Subtarget.useOddSPReg())) {
Sasa Stankovicb976fee2014-07-14 09:40:29 +0000304 unsigned DstReg = I->getOperand(0).getReg();
305 unsigned LoReg = I->getOperand(1).getReg();
306 unsigned HiReg = I->getOperand(2).getReg();
307
308 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000309 // the cases where mthc1 is not available). 64-bit architectures and
310 // MIPS32r2 or later can use FGR64 though.
311 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
312 !Subtarget.isFP64bit());
Sasa Stankovicb976fee2014-07-14 09:40:29 +0000313
314 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000315 const TargetRegisterClass *RC2 =
316 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
Sasa Stankovicb976fee2014-07-14 09:40:29 +0000317
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000318 // We re-use the same spill slot each time so that the stack frame doesn't
319 // grow too much in functions with a large number of moves.
320 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2);
Vasileios Kalintiris167c3722014-10-16 15:41:51 +0000321 if (!Subtarget.isLittle())
322 std::swap(LoReg, HiReg);
Eric Christopher96e72c62015-01-29 23:27:36 +0000323 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
324 &RegInfo, 0);
325 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
326 &RegInfo, 4);
327 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0);
Sasa Stankovicb976fee2014-07-14 09:40:29 +0000328 return true;
329 }
330
331 return false;
332}
333
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000334/// This method expands the same instruction that MipsSEInstrInfo::
335/// expandExtractElementF64 does, for the case when ABI is fpxx and mfhc1 is not
336/// available and the case where the ABI is FP64A. It is implemented here
337/// because frame indexes are eliminated before MipsSEInstrInfo::
338/// expandExtractElementF64 is called.
339bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
340 MachineBasicBlock::iterator I,
341 bool FP64) const {
Daniel Sanders2fb85642015-10-12 13:55:44 +0000342 const MachineOperand &Op1 = I->getOperand(1);
343 const MachineOperand &Op2 = I->getOperand(2);
344
345 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
346 unsigned DstReg = I->getOperand(0).getReg();
347 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
348 return true;
349 }
350
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000351 // For fpxx and when mfhc1 is not available, use:
352 // spill + reload via ldc1
353 //
354 // The case where dmfc1 is available doesn't need to be handled here
355 // because it never creates a ExtractElementF64 node.
356 //
357 // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
358 // for odd-numbered double precision values (because the lower 32-bits is
359 // transferred with mfc1 which is redirected to the upper half of the even
360 // register). Unfortunately, we have to make this decision before register
361 // allocation so for now we use a spill/reload sequence for all
362 // double-precision values in regardless of being an odd/even register.
363
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000364 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
365 (FP64 && !Subtarget.useOddSPReg())) {
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000366 unsigned DstReg = I->getOperand(0).getReg();
Daniel Sanders2fb85642015-10-12 13:55:44 +0000367 unsigned SrcReg = Op1.getReg();
368 unsigned N = Op2.getImm();
Vasileios Kalintiris167c3722014-10-16 15:41:51 +0000369 int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000370
371 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
372 // the cases where mfhc1 is not available). 64-bit architectures and
373 // MIPS32r2 or later can use FGR64 though.
374 assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
375 !Subtarget.isFP64bit());
376
377 const TargetRegisterClass *RC =
378 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
379 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
380
381 // We re-use the same spill slot each time so that the stack frame doesn't
382 // grow too much in functions with a large number of moves.
383 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
Daniel Sanders2fb85642015-10-12 13:55:44 +0000384 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0);
Eric Christopher96e72c62015-01-29 23:27:36 +0000385 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset);
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000386 return true;
387 }
388
389 return false;
390}
391
Eric Christopher4cdb3f92014-07-02 23:29:55 +0000392MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
John Baldwin1255b162017-08-14 21:49:38 +0000393 : MipsFrameLowering(STI, STI.getStackAlignment()) {}
Eric Christopher4cdb3f92014-07-02 23:29:55 +0000394
Quentin Colombet61b305e2015-05-05 17:38:16 +0000395void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
396 MachineBasicBlock &MBB) const {
397 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
Matthias Braun941a7052016-07-28 18:40:00 +0000398 MachineFrameInfo &MFI = MF.getFrameInfo();
Akira Hatanakac0b02062013-01-30 00:26:49 +0000399 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bill Wendlingead89ef2013-06-07 07:04:14 +0000400
Akira Hatanaka88d76cf2012-07-31 23:52:55 +0000401 const MipsSEInstrInfo &TII =
Eric Christopher96e72c62015-01-29 23:27:36 +0000402 *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
403 const MipsRegisterInfo &RegInfo =
404 *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
Bill Wendlingead89ef2013-06-07 07:04:14 +0000405
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000406 MachineBasicBlock::iterator MBBI = MBB.begin();
Petar Jovanovic28e2b712015-08-28 17:53:26 +0000407 DebugLoc dl;
Daniel Sanders81eb66c2015-04-17 09:50:21 +0000408 MipsABIInfo ABI = STI.getABI();
409 unsigned SP = ABI.GetStackPtr();
410 unsigned FP = ABI.GetFramePtr();
411 unsigned ZERO = ABI.GetNullPtr();
Vasileios Kalintiris1c78ca62015-08-11 08:56:25 +0000412 unsigned MOVE = ABI.GetGPRMoveOp();
Vasileios Kalintirisbb698c72015-06-02 13:14:46 +0000413 unsigned ADDiu = ABI.GetPtrAddiuOp();
414 unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;
415
416 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ?
417 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000418
419 // First, compute final stack size.
Matthias Braun941a7052016-07-28 18:40:00 +0000420 uint64_t StackSize = MFI.getStackSize();
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000421
422 // No need to allocate space on the stack.
Matthias Braun941a7052016-07-28 18:40:00 +0000423 if (StackSize == 0 && !MFI.adjustsStack()) return;
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000424
425 MachineModuleInfo &MMI = MF.getMMI();
Bill Wendlingbc07a892013-06-18 07:20:20 +0000426 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000427 MachineLocation DstML, SrcML;
428
429 // Adjust stack.
Akira Hatanaka88d76cf2012-07-31 23:52:55 +0000430 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000431
432 // emit ".cfi_def_cfa_offset StackSize"
Matthias Braunf23ef432016-11-30 23:48:42 +0000433 unsigned CFIIndex = MF.addFrameInst(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000434 MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
435 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
436 .addCFIIndex(CFIIndex);
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000437
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000438 if (MF.getFunction()->hasFnAttribute("interrupt"))
439 emitInterruptPrologueStub(MF, MBB);
440
Matthias Braun941a7052016-07-28 18:40:00 +0000441 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000442
Eugene Zelenko926883e2017-02-01 01:22:51 +0000443 if (!CSI.empty()) {
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000444 // Find the instruction past the last instruction that saves a callee-saved
445 // register to the stack.
446 for (unsigned i = 0; i < CSI.size(); ++i)
447 ++MBBI;
448
449 // Iterate over list of callee-saved registers and emit .cfi_offset
450 // directives.
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000451 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
452 E = CSI.end(); I != E; ++I) {
Matthias Braun941a7052016-07-28 18:40:00 +0000453 int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000454 unsigned Reg = I->getReg();
455
456 // If Reg is a double precision register, emit two cfa_offsets,
457 // one for each of the paired single precision registers.
458 if (Mips::AFGR64RegClass.contains(Reg)) {
Rafael Espindolab08d2c22013-05-16 21:02:15 +0000459 unsigned Reg0 =
Akira Hatanaka14e31a22013-08-20 22:58:56 +0000460 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
Rafael Espindolab08d2c22013-05-16 21:02:15 +0000461 unsigned Reg1 =
Akira Hatanaka14e31a22013-08-20 22:58:56 +0000462 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000463
464 if (!STI.isLittle())
Rafael Espindolab08d2c22013-05-16 21:02:15 +0000465 std::swap(Reg0, Reg1);
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000466
Matthias Braunf23ef432016-11-30 23:48:42 +0000467 unsigned CFIIndex = MF.addFrameInst(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000468 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
469 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
470 .addCFIIndex(CFIIndex);
471
Matthias Braunf23ef432016-11-30 23:48:42 +0000472 CFIIndex = MF.addFrameInst(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000473 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
474 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
475 .addCFIIndex(CFIIndex);
Zoran Jovanovicf34b4542014-07-10 22:23:30 +0000476 } else if (Mips::FGR64RegClass.contains(Reg)) {
477 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
478 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
479
480 if (!STI.isLittle())
481 std::swap(Reg0, Reg1);
482
Matthias Braunf23ef432016-11-30 23:48:42 +0000483 unsigned CFIIndex = MF.addFrameInst(
Zoran Jovanovicf34b4542014-07-10 22:23:30 +0000484 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
485 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
486 .addCFIIndex(CFIIndex);
487
Matthias Braunf23ef432016-11-30 23:48:42 +0000488 CFIIndex = MF.addFrameInst(
Zoran Jovanovicf34b4542014-07-10 22:23:30 +0000489 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
490 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
491 .addCFIIndex(CFIIndex);
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000492 } else {
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000493 // Reg is either in GPR32 or FGR32.
Matthias Braunf23ef432016-11-30 23:48:42 +0000494 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
Eugene Zelenko926883e2017-02-01 01:22:51 +0000495 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000496 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
497 .addCFIIndex(CFIIndex);
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000498 }
499 }
500 }
501
Akira Hatanakac0b02062013-01-30 00:26:49 +0000502 if (MipsFI->callsEhReturn()) {
Akira Hatanakac0b02062013-01-30 00:26:49 +0000503 // Insert instructions that spill eh data registers.
504 for (int I = 0; I < 4; ++I) {
Daniel Sanders81eb66c2015-04-17 09:50:21 +0000505 if (!MBB.isLiveIn(ABI.GetEhDataReg(I)))
506 MBB.addLiveIn(ABI.GetEhDataReg(I));
507 TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false,
Vasileios Kalintirisbb698c72015-06-02 13:14:46 +0000508 MipsFI->getEhDataRegFI(I), RC, &RegInfo);
Akira Hatanakac0b02062013-01-30 00:26:49 +0000509 }
510
511 // Emit .cfi_offset directives for eh data registers.
Akira Hatanakac0b02062013-01-30 00:26:49 +0000512 for (int I = 0; I < 4; ++I) {
Matthias Braun941a7052016-07-28 18:40:00 +0000513 int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I));
Daniel Sanders81eb66c2015-04-17 09:50:21 +0000514 unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true);
Matthias Braunf23ef432016-11-30 23:48:42 +0000515 unsigned CFIIndex = MF.addFrameInst(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000516 MCCFIInstruction::createOffset(nullptr, Reg, Offset));
517 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
518 .addCFIIndex(CFIIndex);
Akira Hatanakac0b02062013-01-30 00:26:49 +0000519 }
520 }
521
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000522 // if framepointer enabled, set it to point to the stack pointer.
523 if (hasFP(MF)) {
524 // Insert instruction "move $fp, $sp" at this location.
Vasileios Kalintiris1c78ca62015-08-11 08:56:25 +0000525 BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
Eric Christopherb45b4812014-04-14 22:21:22 +0000526 .setMIFlag(MachineInstr::FrameSetup);
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000527
528 // emit ".cfi_def_cfa_register $fp"
Matthias Braunf23ef432016-11-30 23:48:42 +0000529 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000530 nullptr, MRI->getDwarfRegNum(FP, true)));
531 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
532 .addCFIIndex(CFIIndex);
Vasileios Kalintirisbb698c72015-06-02 13:14:46 +0000533
534 if (RegInfo.needsStackRealignment(MF)) {
535 // addiu $Reg, $zero, -MaxAlignment
536 // andi $sp, $sp, $Reg
537 unsigned VR = MF.getRegInfo().createVirtualRegister(RC);
Matthias Braun941a7052016-07-28 18:40:00 +0000538 assert(isInt<16>(MFI.getMaxAlignment()) &&
Vasileios Kalintirisbb698c72015-06-02 13:14:46 +0000539 "Function's alignment size requirement is not supported.");
Matthias Braun941a7052016-07-28 18:40:00 +0000540 int MaxAlign = -(int)MFI.getMaxAlignment();
Vasileios Kalintirisbb698c72015-06-02 13:14:46 +0000541
542 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
543 BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
544
545 if (hasBP(MF)) {
546 // move $s7, $sp
547 unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;
Vasileios Kalintiris1c78ca62015-08-11 08:56:25 +0000548 BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP)
Vasileios Kalintirisbb698c72015-06-02 13:14:46 +0000549 .addReg(SP)
550 .addReg(ZERO);
551 }
552 }
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000553 }
554}
555
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000556void MipsSEFrameLowering::emitInterruptPrologueStub(
557 MachineFunction &MF, MachineBasicBlock &MBB) const {
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000558 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
559 MachineBasicBlock::iterator MBBI = MBB.begin();
560 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
561
562 // Report an error the target doesn't support Mips32r2 or later.
563 // The epilogue relies on the use of the "ehb" to clear execution
564 // hazards. Pre R2 Mips relies on an implementation defined number
565 // of "ssnop"s to clear the execution hazard. Support for ssnop hazard
566 // clearing is not provided so reject that configuration.
567 if (!STI.hasMips32r2())
568 report_fatal_error(
Vasileios Kalintiris165121f2015-10-26 14:24:30 +0000569 "\"interrupt\" attribute is not supported on pre-MIPS32R2 or "
570 "MIPS16 targets.");
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000571
572 // The GP register contains the "user" value, so we cannot perform
573 // any gp relative loads until we restore the "kernel" or "system" gp
574 // value. Until support is written we shall only accept the static
575 // relocation model.
576 if ((STI.getRelocationModel() != Reloc::Static))
577 report_fatal_error("\"interrupt\" attribute is only supported for the "
578 "static relocation model on MIPS at the present time.");
579
580 if (!STI.isABI_O32() || STI.hasMips64())
581 report_fatal_error("\"interrupt\" attribute is only supported for the "
Vasileios Kalintiris165121f2015-10-26 14:24:30 +0000582 "O32 ABI on MIPS32R2+ at the present time.");
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000583
584 // Perform ISR handling like GCC
585 StringRef IntKind =
586 MF.getFunction()->getFnAttribute("interrupt").getValueAsString();
587 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
588
589 // EIC interrupt handling needs to read the Cause register to disable
590 // interrupts.
591 if (IntKind == "eic") {
592 // Coprocessor registers are always live per se.
593 MBB.addLiveIn(Mips::COP013);
594 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)
595 .addReg(Mips::COP013)
596 .addImm(0)
597 .setMIFlag(MachineInstr::FrameSetup);
598
599 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)
600 .addReg(Mips::K0)
601 .addImm(10)
602 .addImm(6)
603 .setMIFlag(MachineInstr::FrameSetup);
604 }
605
606 // Fetch and spill EPC
607 MBB.addLiveIn(Mips::COP014);
608 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
609 .addReg(Mips::COP014)
610 .addImm(0)
611 .setMIFlag(MachineInstr::FrameSetup);
612
613 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
614 MipsFI->getISRRegFI(0), PtrRC,
615 STI.getRegisterInfo(), 0);
616
617 // Fetch and Spill Status
618 MBB.addLiveIn(Mips::COP012);
619 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
620 .addReg(Mips::COP012)
621 .addImm(0)
622 .setMIFlag(MachineInstr::FrameSetup);
623
624 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
625 MipsFI->getISRRegFI(1), PtrRC,
626 STI.getRegisterInfo(), 0);
627
628 // Build the configuration for disabling lower priority interrupts. Non EIC
629 // interrupts need to be masked off with zero, EIC from the Cause register.
630 unsigned InsPosition = 8;
631 unsigned InsSize = 0;
632 unsigned SrcReg = Mips::ZERO;
633
634 // If the interrupt we're tied to is the EIC, switch the source for the
635 // masking off interrupts to the cause register.
636 if (IntKind == "eic") {
637 SrcReg = Mips::K0;
638 InsPosition = 10;
639 InsSize = 6;
640 } else
641 InsSize = StringSwitch<unsigned>(IntKind)
642 .Case("sw0", 1)
643 .Case("sw1", 2)
644 .Case("hw0", 3)
645 .Case("hw1", 4)
646 .Case("hw2", 5)
647 .Case("hw3", 6)
648 .Case("hw4", 7)
649 .Case("hw5", 8)
650 .Default(0);
651 assert(InsSize != 0 && "Unknown interrupt type!");
652
653 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
654 .addReg(SrcReg)
655 .addImm(InsPosition)
656 .addImm(InsSize)
657 .addReg(Mips::K1)
658 .setMIFlag(MachineInstr::FrameSetup);
659
660 // Mask off KSU, ERL, EXL
661 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
662 .addReg(Mips::ZERO)
663 .addImm(1)
664 .addImm(4)
665 .addReg(Mips::K1)
666 .setMIFlag(MachineInstr::FrameSetup);
667
668 // Disable the FPU as we are not spilling those register sets.
669 if (!STI.useSoftFloat())
670 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
671 .addReg(Mips::ZERO)
672 .addImm(29)
673 .addImm(1)
674 .addReg(Mips::K1)
675 .setMIFlag(MachineInstr::FrameSetup);
676
677 // Set the new status
678 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
679 .addReg(Mips::K1)
680 .addImm(0)
681 .setMIFlag(MachineInstr::FrameSetup);
682}
683
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000684void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
685 MachineBasicBlock &MBB) const {
686 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
Matthias Braun941a7052016-07-28 18:40:00 +0000687 MachineFrameInfo &MFI = MF.getFrameInfo();
Akira Hatanakac0b02062013-01-30 00:26:49 +0000688 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bill Wendlingead89ef2013-06-07 07:04:14 +0000689
Akira Hatanaka88d76cf2012-07-31 23:52:55 +0000690 const MipsSEInstrInfo &TII =
Eric Christopher96e72c62015-01-29 23:27:36 +0000691 *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
692 const MipsRegisterInfo &RegInfo =
693 *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
Bill Wendlingead89ef2013-06-07 07:04:14 +0000694
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000695 DebugLoc DL = MBBI->getDebugLoc();
Daniel Sanders81eb66c2015-04-17 09:50:21 +0000696 MipsABIInfo ABI = STI.getABI();
697 unsigned SP = ABI.GetStackPtr();
698 unsigned FP = ABI.GetFramePtr();
699 unsigned ZERO = ABI.GetNullPtr();
Vasileios Kalintiris1c78ca62015-08-11 08:56:25 +0000700 unsigned MOVE = ABI.GetGPRMoveOp();
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000701
702 // if framepointer enabled, restore the stack pointer.
703 if (hasFP(MF)) {
704 // Find the first instruction that restores a callee-saved register.
705 MachineBasicBlock::iterator I = MBBI;
706
Matthias Braun941a7052016-07-28 18:40:00 +0000707 for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i)
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000708 --I;
709
710 // Insert instruction "move $sp, $fp" at this location.
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000711 BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000712 }
713
Akira Hatanakac0b02062013-01-30 00:26:49 +0000714 if (MipsFI->callsEhReturn()) {
Daniel Sanders81eb66c2015-04-17 09:50:21 +0000715 const TargetRegisterClass *RC =
716 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
Akira Hatanakac0b02062013-01-30 00:26:49 +0000717
718 // Find first instruction that restores a callee-saved register.
719 MachineBasicBlock::iterator I = MBBI;
Matthias Braun941a7052016-07-28 18:40:00 +0000720 for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i)
Akira Hatanakac0b02062013-01-30 00:26:49 +0000721 --I;
722
723 // Insert instructions that restore eh data registers.
724 for (int J = 0; J < 4; ++J) {
Daniel Sanders81eb66c2015-04-17 09:50:21 +0000725 TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J),
726 MipsFI->getEhDataRegFI(J), RC, &RegInfo);
Akira Hatanakac0b02062013-01-30 00:26:49 +0000727 }
728 }
729
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000730 if (MF.getFunction()->hasFnAttribute("interrupt"))
731 emitInterruptEpilogueStub(MF, MBB);
732
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000733 // Get the number of bytes from FrameInfo
Matthias Braun941a7052016-07-28 18:40:00 +0000734 uint64_t StackSize = MFI.getStackSize();
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000735
736 if (!StackSize)
737 return;
738
739 // Adjust stack.
Akira Hatanaka88d76cf2012-07-31 23:52:55 +0000740 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000741}
742
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000743void MipsSEFrameLowering::emitInterruptEpilogueStub(
744 MachineFunction &MF, MachineBasicBlock &MBB) const {
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000745 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
746 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
747 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
748
749 // Perform ISR handling like GCC
750 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
751
752 // Disable Interrupts.
753 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
754 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
755
756 // Restore EPC
757 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
758 MipsFI->getISRRegFI(0), PtrRC,
759 STI.getRegisterInfo());
760 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
761 .addReg(Mips::K1)
762 .addImm(0);
763
764 // Restore Status
765 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
766 MipsFI->getISRRegFI(1), PtrRC,
767 STI.getRegisterInfo());
768 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
769 .addReg(Mips::K1)
770 .addImm(0);
771}
772
Vasileios Kalintiris48e02562015-11-12 14:11:43 +0000773int MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF,
774 int FI,
775 unsigned &FrameReg) const {
Matthias Braun941a7052016-07-28 18:40:00 +0000776 const MachineFrameInfo &MFI = MF.getFrameInfo();
Vasileios Kalintiris48e02562015-11-12 14:11:43 +0000777 MipsABIInfo ABI = STI.getABI();
778
Matthias Braun941a7052016-07-28 18:40:00 +0000779 if (MFI.isFixedObjectIndex(FI))
Vasileios Kalintiris48e02562015-11-12 14:11:43 +0000780 FrameReg = hasFP(MF) ? ABI.GetFramePtr() : ABI.GetStackPtr();
781 else
782 FrameReg = hasBP(MF) ? ABI.GetBasePtr() : ABI.GetStackPtr();
783
Matthias Braun941a7052016-07-28 18:40:00 +0000784 return MFI.getObjectOffset(FI) + MFI.getStackSize() -
785 getOffsetOfLocalArea() + MFI.getOffsetAdjustment();
Vasileios Kalintiris48e02562015-11-12 14:11:43 +0000786}
787
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000788bool MipsSEFrameLowering::
789spillCalleeSavedRegisters(MachineBasicBlock &MBB,
790 MachineBasicBlock::iterator MI,
791 const std::vector<CalleeSavedInfo> &CSI,
792 const TargetRegisterInfo *TRI) const {
793 MachineFunction *MF = MBB.getParent();
Duncan P. N. Exon Smith78691482015-10-20 00:15:20 +0000794 MachineBasicBlock *EntryBlock = &MF->front();
Eric Christopher96e72c62015-01-29 23:27:36 +0000795 const TargetInstrInfo &TII = *STI.getInstrInfo();
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000796
797 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
798 // Add the callee-saved register as live-in. Do not add if the register is
799 // RA and return address is taken, because it has already been added in
Daniel Sanders94ed30a2016-07-26 14:46:11 +0000800 // method MipsTargetLowering::lowerRETURNADDR.
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000801 // It's killed at the spill, unless the register is RA and return address
802 // is taken.
803 unsigned Reg = CSI[i].getReg();
804 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
Matthias Braun941a7052016-07-28 18:40:00 +0000805 && MF->getFrameInfo().isReturnAddressTaken();
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000806 if (!IsRAAndRetAddrIsTaken)
807 EntryBlock->addLiveIn(Reg);
808
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000809 // ISRs require HI/LO to be spilled into kernel registers to be then
810 // spilled to the stack frame.
811 bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 ||
812 Reg == Mips::HI0 || Reg == Mips::HI0_64);
813 const Function *Func = MBB.getParent()->getFunction();
814 if (IsLOHI && Func->hasFnAttribute("interrupt")) {
815 DebugLoc DL = MI->getDebugLoc();
816
817 unsigned Op = 0;
818 if (!STI.getABI().ArePtrs64bit()) {
819 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;
820 Reg = Mips::K0;
821 } else {
822 Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64;
823 Reg = Mips::K0_64;
824 }
825 BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
826 .setMIFlag(MachineInstr::FrameSetup);
827 }
828
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000829 // Insert the spill to the stack frame.
830 bool IsKill = !IsRAAndRetAddrIsTaken;
831 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
832 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
833 CSI[i].getFrameIdx(), RC, TRI);
834 }
835
836 return true;
837}
838
839bool
840MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
Matthias Braun941a7052016-07-28 18:40:00 +0000841 const MachineFrameInfo &MFI = MF.getFrameInfo();
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000842 // Reserve call frame if the size of the maximum call frame fits into 16-bit
843 // immediate field and there are no variable sized objects on the stack.
Akira Hatanaka3b701452013-03-30 01:04:11 +0000844 // Make sure the second register scavenger spill slot can be accessed with one
845 // instruction.
Matthias Braun941a7052016-07-28 18:40:00 +0000846 return isInt<16>(MFI.getMaxCallFrameSize() + getStackAlignment()) &&
847 !MFI.hasVarSizedObjects();
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000848}
849
Matthias Braun02564862015-07-14 17:17:13 +0000850/// Mark \p Reg and all registers aliasing it in the bitset.
Benjamin Kramer7d54fab2015-07-16 11:12:05 +0000851static void setAliasRegs(MachineFunction &MF, BitVector &SavedRegs,
852 unsigned Reg) {
Matthias Braun02564862015-07-14 17:17:13 +0000853 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
854 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
855 SavedRegs.set(*AI);
856}
857
858void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
859 BitVector &SavedRegs,
860 RegScavenger *RS) const {
861 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
Krzysztof Parzyszek44e25f32017-04-24 18:55:33 +0000862 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
Akira Hatanakac0b02062013-01-30 00:26:49 +0000863 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Daniel Sanders81eb66c2015-04-17 09:50:21 +0000864 MipsABIInfo ABI = STI.getABI();
865 unsigned FP = ABI.GetFramePtr();
Vasileios Kalintirisbb698c72015-06-02 13:14:46 +0000866 unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7;
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000867
868 // Mark $fp as used if function has dedicated frame pointer.
869 if (hasFP(MF))
Matthias Braun02564862015-07-14 17:17:13 +0000870 setAliasRegs(MF, SavedRegs, FP);
Vasileios Kalintirisbb698c72015-06-02 13:14:46 +0000871 // Mark $s7 as used if function has dedicated base pointer.
872 if (hasBP(MF))
Matthias Braun02564862015-07-14 17:17:13 +0000873 setAliasRegs(MF, SavedRegs, BP);
Akira Hatanaka5852e3b2012-11-03 00:05:43 +0000874
Akira Hatanakac0b02062013-01-30 00:26:49 +0000875 // Create spill slots for eh data registers if function calls eh_return.
876 if (MipsFI->callsEhReturn())
877 MipsFI->createEhDataRegsFI();
878
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000879 // Create spill slots for Coprocessor 0 registers if function is an ISR.
880 if (MipsFI->isISR())
881 MipsFI->createISRRegFI();
882
Akira Hatanaka3b701452013-03-30 01:04:11 +0000883 // Expand pseudo instructions which load, store or copy accumulators.
884 // Add an emergency spill slot if a pseudo was expanded.
Akira Hatanakaae4a5562013-05-01 23:41:31 +0000885 if (ExpandPseudo(MF).expand()) {
Akira Hatanaka3b701452013-03-30 01:04:11 +0000886 // The spill slot should be half the size of the accumulator. If target is
887 // mips64, it should be 64-bit, otherwise it should be 32-bt.
Krzysztof Parzyszek44e25f32017-04-24 18:55:33 +0000888 const TargetRegisterClass &RC = STI.hasMips64() ?
889 Mips::GPR64RegClass : Mips::GPR32RegClass;
890 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
891 TRI->getSpillAlignment(RC),
892 false);
Akira Hatanaka3b701452013-03-30 01:04:11 +0000893 RS->addScavengingFrameIndex(FI);
894 }
895
Akira Hatanaka5852e3b2012-11-03 00:05:43 +0000896 // Set scavenging frame index if necessary.
897 uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
898 estimateStackSize(MF);
899
900 if (isInt<16>(MaxSPOffset))
901 return;
902
Krzysztof Parzyszek44e25f32017-04-24 18:55:33 +0000903 const TargetRegisterClass &RC =
904 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass;
905 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
906 TRI->getSpillAlignment(RC),
907 false);
Hal Finkel9e331c22013-03-22 23:32:27 +0000908 RS->addScavengingFrameIndex(FI);
Akira Hatanakad1c43ce2012-07-31 22:50:19 +0000909}
Akira Hatanakafab89292012-08-02 18:21:47 +0000910
911const MipsFrameLowering *
912llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
913 return new MipsSEFrameLowering(ST);
914}