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gerrit-public.fairphone.software / toolchain / llvm-project / db4c21f9945283f2e8d29c7a8a898512ebf37b52 / . / llvm / test / CodeGen / Mips / msa / bitwise.ll
blob: 0d4407388c17182ba1bfd32685ef9fe9e9d08ed9 [file] [log] [blame]
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame]1; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
2
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]3define void @and_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
4 ; CHECK: and_v16i8:
5
6 %1 = load <16 x i8>* %a
7 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
8 %2 = load <16 x i8>* %b
9 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
10 %3 = and <16 x i8> %1, %2
11 ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
12 store <16 x i8> %3, <16 x i8>* %c
13 ; CHECK-DAG: st.b [[R3]], 0($4)
14
15 ret void
16 ; CHECK: .size and_v16i8
17}
18
19define void @and_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
20 ; CHECK: and_v8i16:
21
22 %1 = load <8 x i16>* %a
23 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
24 %2 = load <8 x i16>* %b
25 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
26 %3 = and <8 x i16> %1, %2
27 ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
28 store <8 x i16> %3, <8 x i16>* %c
29 ; CHECK-DAG: st.h [[R3]], 0($4)
30
31 ret void
32 ; CHECK: .size and_v8i16
33}
34
35define void @and_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
36 ; CHECK: and_v4i32:
37
38 %1 = load <4 x i32>* %a
39 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
40 %2 = load <4 x i32>* %b
41 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
42 %3 = and <4 x i32> %1, %2
43 ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
44 store <4 x i32> %3, <4 x i32>* %c
45 ; CHECK-DAG: st.w [[R3]], 0($4)
46
47 ret void
48 ; CHECK: .size and_v4i32
49}
50
51define void @and_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
52 ; CHECK: and_v2i64:
53
54 %1 = load <2 x i64>* %a
55 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
56 %2 = load <2 x i64>* %b
57 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
58 %3 = and <2 x i64> %1, %2
59 ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
60 store <2 x i64> %3, <2 x i64>* %c
61 ; CHECK-DAG: st.d [[R3]], 0($4)
62
63 ret void
64 ; CHECK: .size and_v2i64
65}
66
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]67define void @and_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
68 ; CHECK: and_v16i8_i:
69
70 %1 = load <16 x i8>* %a
71 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
72 %2 = and <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
73 ; CHECK-DAG: andi.b [[R4:\$w[0-9]+]], [[R1]], 1
74 store <16 x i8> %2, <16 x i8>* %c
75 ; CHECK-DAG: st.b [[R4]], 0($4)
76
77 ret void
78 ; CHECK: .size and_v16i8_i
79}
80
81define void @and_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
82 ; CHECK: and_v8i16_i:
83
84 %1 = load <8 x i16>* %a
85 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
86 %2 = and <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
87 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
88 ; CHECK-DAG: and.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
89 store <8 x i16> %2, <8 x i16>* %c
90 ; CHECK-DAG: st.h [[R4]], 0($4)
91
92 ret void
93 ; CHECK: .size and_v8i16_i
94}
95
96define void @and_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
97 ; CHECK: and_v4i32_i:
98
99 %1 = load <4 x i32>* %a
100 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
101 %2 = and <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
102 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
103 ; CHECK-DAG: and.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
104 store <4 x i32> %2, <4 x i32>* %c
105 ; CHECK-DAG: st.w [[R4]], 0($4)
106
107 ret void
108 ; CHECK: .size and_v4i32_i
109}
110
111define void @and_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
112 ; CHECK: and_v2i64_i:
113
114 %1 = load <2 x i64>* %a
115 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
116 %2 = and <2 x i64> %1, <i64 1, i64 1>
117 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
118 ; CHECK-DAG: and.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
119 store <2 x i64> %2, <2 x i64>* %c
120 ; CHECK-DAG: st.d [[R4]], 0($4)
121
122 ret void
123 ; CHECK: .size and_v2i64_i
124}
125
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]126define void @or_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
127 ; CHECK: or_v16i8:
128
129 %1 = load <16 x i8>* %a
130 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
131 %2 = load <16 x i8>* %b
132 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
133 %3 = or <16 x i8> %1, %2
134 ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
135 store <16 x i8> %3, <16 x i8>* %c
136 ; CHECK-DAG: st.b [[R3]], 0($4)
137
138 ret void
139 ; CHECK: .size or_v16i8
140}
141
142define void @or_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
143 ; CHECK: or_v8i16:
144
145 %1 = load <8 x i16>* %a
146 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
147 %2 = load <8 x i16>* %b
148 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
149 %3 = or <8 x i16> %1, %2
150 ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
151 store <8 x i16> %3, <8 x i16>* %c
152 ; CHECK-DAG: st.h [[R3]], 0($4)
153
154 ret void
155 ; CHECK: .size or_v8i16
156}
157
158define void @or_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
159 ; CHECK: or_v4i32:
160
161 %1 = load <4 x i32>* %a
162 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
163 %2 = load <4 x i32>* %b
164 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
165 %3 = or <4 x i32> %1, %2
166 ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
167 store <4 x i32> %3, <4 x i32>* %c
168 ; CHECK-DAG: st.w [[R3]], 0($4)
169
170 ret void
171 ; CHECK: .size or_v4i32
172}
173
174define void @or_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
175 ; CHECK: or_v2i64:
176
177 %1 = load <2 x i64>* %a
178 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
179 %2 = load <2 x i64>* %b
180 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
181 %3 = or <2 x i64> %1, %2
182 ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
183 store <2 x i64> %3, <2 x i64>* %c
184 ; CHECK-DAG: st.d [[R3]], 0($4)
185
186 ret void
187 ; CHECK: .size or_v2i64
188}
189
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]190define void @or_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
191 ; CHECK: or_v16i8_i:
192
193 %1 = load <16 x i8>* %a
194 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
195 %2 = or <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
196 ; CHECK-DAG: ori.b [[R4:\$w[0-9]+]], [[R1]], 1
197 store <16 x i8> %2, <16 x i8>* %c
198 ; CHECK-DAG: st.b [[R4]], 0($4)
199
200 ret void
201 ; CHECK: .size or_v16i8_i
202}
203
204define void @or_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
205 ; CHECK: or_v8i16_i:
206
207 %1 = load <8 x i16>* %a
208 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
209 %2 = or <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
210 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
211 ; CHECK-DAG: or.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
212 store <8 x i16> %2, <8 x i16>* %c
213 ; CHECK-DAG: st.h [[R4]], 0($4)
214
215 ret void
216 ; CHECK: .size or_v8i16_i
217}
218
219define void @or_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
220 ; CHECK: or_v4i32_i:
221
222 %1 = load <4 x i32>* %a
223 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
224 %2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
225 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
226 ; CHECK-DAG: or.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
227 store <4 x i32> %2, <4 x i32>* %c
228 ; CHECK-DAG: st.w [[R4]], 0($4)
229
230 ret void
231 ; CHECK: .size or_v4i32_i
232}
233
234define void @or_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
235 ; CHECK: or_v2i64_i:
236
237 %1 = load <2 x i64>* %a
238 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
239 %2 = or <2 x i64> %1, <i64 1, i64 1>
240 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
241 ; CHECK-DAG: or.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
242 store <2 x i64> %2, <2 x i64>* %c
243 ; CHECK-DAG: st.d [[R4]], 0($4)
244
245 ret void
246 ; CHECK: .size or_v2i64_i
247}
248
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]249define void @nor_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
250 ; CHECK: nor_v16i8:
251
252 %1 = load <16 x i8>* %a
253 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
254 %2 = load <16 x i8>* %b
255 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
256 %3 = or <16 x i8> %1, %2
257 %4 = xor <16 x i8> %3, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
258 ; CHECK-DAG: nor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
259 store <16 x i8> %4, <16 x i8>* %c
260 ; CHECK-DAG: st.b [[R3]], 0($4)
261
262 ret void
263 ; CHECK: .size nor_v16i8
264}
265
266define void @nor_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
267 ; CHECK: nor_v8i16:
268
269 %1 = load <8 x i16>* %a
270 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
271 %2 = load <8 x i16>* %b
272 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
273 %3 = or <8 x i16> %1, %2
274 %4 = xor <8 x i16> %3, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
275 ; CHECK-DAG: nor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
276 store <8 x i16> %4, <8 x i16>* %c
277 ; CHECK-DAG: st.h [[R3]], 0($4)
278
279 ret void
280 ; CHECK: .size nor_v8i16
281}
282
283define void @nor_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
284 ; CHECK: nor_v4i32:
285
286 %1 = load <4 x i32>* %a
287 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
288 %2 = load <4 x i32>* %b
289 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
290 %3 = or <4 x i32> %1, %2
291 %4 = xor <4 x i32> %3, <i32 -1, i32 -1, i32 -1, i32 -1>
292 ; CHECK-DAG: nor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
293 store <4 x i32> %4, <4 x i32>* %c
294 ; CHECK-DAG: st.w [[R3]], 0($4)
295
296 ret void
297 ; CHECK: .size nor_v4i32
298}
299
300define void @nor_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
301 ; CHECK: nor_v2i64:
302
303 %1 = load <2 x i64>* %a
304 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
305 %2 = load <2 x i64>* %b
306 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
307 %3 = or <2 x i64> %1, %2
308 %4 = xor <2 x i64> %3, <i64 -1, i64 -1>
309 ; CHECK-DAG: nor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
310 store <2 x i64> %4, <2 x i64>* %c
311 ; CHECK-DAG: st.d [[R3]], 0($4)
312
313 ret void
314 ; CHECK: .size nor_v2i64
315}
316
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]317define void @nor_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
318 ; CHECK: nor_v16i8_i:
319
320 %1 = load <16 x i8>* %a
321 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
322 %2 = or <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
323 %3 = xor <16 x i8> %2, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
324 ; CHECK-DAG: ori.b [[R4:\$w[0-9]+]], [[R1]], 1
325 store <16 x i8> %3, <16 x i8>* %c
326 ; CHECK-DAG: st.b [[R4]], 0($4)
327
328 ret void
329 ; CHECK: .size nor_v16i8_i
330}
331
332define void @nor_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
333 ; CHECK: nor_v8i16_i:
334
335 %1 = load <8 x i16>* %a
336 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
337 %2 = or <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
338 %3 = xor <8 x i16> %2, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
339 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
340 ; CHECK-DAG: nor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
341 store <8 x i16> %3, <8 x i16>* %c
342 ; CHECK-DAG: st.h [[R4]], 0($4)
343
344 ret void
345 ; CHECK: .size nor_v8i16_i
346}
347
348define void @nor_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
349 ; CHECK: nor_v4i32_i:
350
351 %1 = load <4 x i32>* %a
352 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
353 %2 = or <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
354 %3 = xor <4 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1>
355 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
356 ; CHECK-DAG: nor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
357 store <4 x i32> %3, <4 x i32>* %c
358 ; CHECK-DAG: st.w [[R4]], 0($4)
359
360 ret void
361 ; CHECK: .size nor_v4i32_i
362}
363
364define void @nor_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
365 ; CHECK: nor_v2i64_i:
366
367 %1 = load <2 x i64>* %a
368 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
369 %2 = or <2 x i64> %1, <i64 1, i64 1>
370 %3 = xor <2 x i64> %2, <i64 -1, i64 -1>
371 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
372 ; CHECK-DAG: nor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
373 store <2 x i64> %3, <2 x i64>* %c
374 ; CHECK-DAG: st.d [[R4]], 0($4)
375
376 ret void
377 ; CHECK: .size nor_v2i64_i
378}
379
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]380define void @xor_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
381 ; CHECK: xor_v16i8:
382
383 %1 = load <16 x i8>* %a
384 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
385 %2 = load <16 x i8>* %b
386 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
387 %3 = xor <16 x i8> %1, %2
388 ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
389 store <16 x i8> %3, <16 x i8>* %c
390 ; CHECK-DAG: st.b [[R3]], 0($4)
391
392 ret void
393 ; CHECK: .size xor_v16i8
394}
395
396define void @xor_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
397 ; CHECK: xor_v8i16:
398
399 %1 = load <8 x i16>* %a
400 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
401 %2 = load <8 x i16>* %b
402 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
403 %3 = xor <8 x i16> %1, %2
404 ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
405 store <8 x i16> %3, <8 x i16>* %c
406 ; CHECK-DAG: st.h [[R3]], 0($4)
407
408 ret void
409 ; CHECK: .size xor_v8i16
410}
411
412define void @xor_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
413 ; CHECK: xor_v4i32:
414
415 %1 = load <4 x i32>* %a
416 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
417 %2 = load <4 x i32>* %b
418 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
419 %3 = xor <4 x i32> %1, %2
420 ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
421 store <4 x i32> %3, <4 x i32>* %c
422 ; CHECK-DAG: st.w [[R3]], 0($4)
423
424 ret void
425 ; CHECK: .size xor_v4i32
426}
427
428define void @xor_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
429 ; CHECK: xor_v2i64:
430
431 %1 = load <2 x i64>* %a
432 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
433 %2 = load <2 x i64>* %b
434 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
435 %3 = xor <2 x i64> %1, %2
436 ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
437 store <2 x i64> %3, <2 x i64>* %c
438 ; CHECK-DAG: st.d [[R3]], 0($4)
439
440 ret void
441 ; CHECK: .size xor_v2i64
442}
443
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]444define void @xor_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
445 ; CHECK: xor_v16i8_i:
446
447 %1 = load <16 x i8>* %a
448 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
449 %2 = xor <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
450 ; CHECK-DAG: xori.b [[R4:\$w[0-9]+]], [[R1]], 1
451 store <16 x i8> %2, <16 x i8>* %c
452 ; CHECK-DAG: st.b [[R4]], 0($4)
453
454 ret void
455 ; CHECK: .size xor_v16i8_i
456}
457
458define void @xor_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
459 ; CHECK: xor_v8i16_i:
460
461 %1 = load <8 x i16>* %a
462 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
463 %2 = xor <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
464 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
465 ; CHECK-DAG: xor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
466 store <8 x i16> %2, <8 x i16>* %c
467 ; CHECK-DAG: st.h [[R4]], 0($4)
468
469 ret void
470 ; CHECK: .size xor_v8i16_i
471}
472
473define void @xor_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
474 ; CHECK: xor_v4i32_i:
475
476 %1 = load <4 x i32>* %a
477 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
478 %2 = xor <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
479 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
480 ; CHECK-DAG: xor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
481 store <4 x i32> %2, <4 x i32>* %c
482 ; CHECK-DAG: st.w [[R4]], 0($4)
483
484 ret void
485 ; CHECK: .size xor_v4i32_i
486}
487
488define void @xor_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
489 ; CHECK: xor_v2i64_i:
490
491 %1 = load <2 x i64>* %a
492 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
493 %2 = xor <2 x i64> %1, <i64 1, i64 1>
494 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
495 ; CHECK-DAG: xor.v [[R4:\$w[0-9]+]], [[R1]], [[R3]]
496 store <2 x i64> %2, <2 x i64>* %c
497 ; CHECK-DAG: st.d [[R4]], 0($4)
498
499 ret void
500 ; CHECK: .size xor_v2i64_i
501}
502
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame]503define void @sll_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
504 ; CHECK: sll_v16i8:
505
506 %1 = load <16 x i8>* %a
507 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
508 %2 = load <16 x i8>* %b
509 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
510 %3 = shl <16 x i8> %1, %2
511 ; CHECK-DAG: sll.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
512 store <16 x i8> %3, <16 x i8>* %c
513 ; CHECK-DAG: st.b [[R3]], 0($4)
514
515 ret void
516 ; CHECK: .size sll_v16i8
517}
518
519define void @sll_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
520 ; CHECK: sll_v8i16:
521
522 %1 = load <8 x i16>* %a
523 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
524 %2 = load <8 x i16>* %b
525 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
526 %3 = shl <8 x i16> %1, %2
527 ; CHECK-DAG: sll.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
528 store <8 x i16> %3, <8 x i16>* %c
529 ; CHECK-DAG: st.h [[R3]], 0($4)
530
531 ret void
532 ; CHECK: .size sll_v8i16
533}
534
535define void @sll_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
536 ; CHECK: sll_v4i32:
537
538 %1 = load <4 x i32>* %a
539 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
540 %2 = load <4 x i32>* %b
541 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
542 %3 = shl <4 x i32> %1, %2
543 ; CHECK-DAG: sll.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
544 store <4 x i32> %3, <4 x i32>* %c
545 ; CHECK-DAG: st.w [[R3]], 0($4)
546
547 ret void
548 ; CHECK: .size sll_v4i32
549}
550
551define void @sll_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
552 ; CHECK: sll_v2i64:
553
554 %1 = load <2 x i64>* %a
555 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
556 %2 = load <2 x i64>* %b
557 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
558 %3 = shl <2 x i64> %1, %2
559 ; CHECK-DAG: sll.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
560 store <2 x i64> %3, <2 x i64>* %c
561 ; CHECK-DAG: st.d [[R3]], 0($4)
562
563 ret void
564 ; CHECK: .size sll_v2i64
565}
566
Daniel Sanderscba19222013-09-24 10:28:18 +0000[diff] [blame]567define void @sll_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
568 ; CHECK: sll_v16i8_i:
569
570 %1 = load <16 x i8>* %a
571 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
572 %2 = shl <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
573 ; CHECK-DAG: slli.b [[R4:\$w[0-9]+]], [[R1]], 1
574 store <16 x i8> %2, <16 x i8>* %c
575 ; CHECK-DAG: st.b [[R4]], 0($4)
576
577 ret void
578 ; CHECK: .size sll_v16i8_i
579}
580
581define void @sll_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
582 ; CHECK: sll_v8i16_i:
583
584 %1 = load <8 x i16>* %a
585 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
586 %2 = shl <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
587 ; CHECK-DAG: slli.h [[R4:\$w[0-9]+]], [[R1]], 1
588 store <8 x i16> %2, <8 x i16>* %c
589 ; CHECK-DAG: st.h [[R4]], 0($4)
590
591 ret void
592 ; CHECK: .size sll_v8i16_i
593}
594
595define void @sll_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
596 ; CHECK: sll_v4i32_i:
597
598 %1 = load <4 x i32>* %a
599 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
600 %2 = shl <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
601 ; CHECK-DAG: slli.w [[R4:\$w[0-9]+]], [[R1]], 1
602 store <4 x i32> %2, <4 x i32>* %c
603 ; CHECK-DAG: st.w [[R4]], 0($4)
604
605 ret void
606 ; CHECK: .size sll_v4i32_i
607}
608
609define void @sll_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
610 ; CHECK: sll_v2i64_i:
611
612 %1 = load <2 x i64>* %a
613 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
614 %2 = shl <2 x i64> %1, <i64 1, i64 1>
615 ; CHECK-DAG: slli.d [[R4:\$w[0-9]+]], [[R1]], 1
616 store <2 x i64> %2, <2 x i64>* %c
617 ; CHECK-DAG: st.d [[R4]], 0($4)
618
619 ret void
620 ; CHECK: .size sll_v2i64_i
621}
622
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame]623define void @sra_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
624 ; CHECK: sra_v16i8:
625
626 %1 = load <16 x i8>* %a
627 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
628 %2 = load <16 x i8>* %b
629 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
630 %3 = ashr <16 x i8> %1, %2
631 ; CHECK-DAG: sra.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
632 store <16 x i8> %3, <16 x i8>* %c
633 ; CHECK-DAG: st.b [[R3]], 0($4)
634
635 ret void
636 ; CHECK: .size sra_v16i8
637}
638
639define void @sra_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
640 ; CHECK: sra_v8i16:
641
642 %1 = load <8 x i16>* %a
643 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
644 %2 = load <8 x i16>* %b
645 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
646 %3 = ashr <8 x i16> %1, %2
647 ; CHECK-DAG: sra.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
648 store <8 x i16> %3, <8 x i16>* %c
649 ; CHECK-DAG: st.h [[R3]], 0($4)
650
651 ret void
652 ; CHECK: .size sra_v8i16
653}
654
655define void @sra_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
656 ; CHECK: sra_v4i32:
657
658 %1 = load <4 x i32>* %a
659 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
660 %2 = load <4 x i32>* %b
661 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
662 %3 = ashr <4 x i32> %1, %2
663 ; CHECK-DAG: sra.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
664 store <4 x i32> %3, <4 x i32>* %c
665 ; CHECK-DAG: st.w [[R3]], 0($4)
666
667 ret void
668 ; CHECK: .size sra_v4i32
669}
670
671define void @sra_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
672 ; CHECK: sra_v2i64:
673
674 %1 = load <2 x i64>* %a
675 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
676 %2 = load <2 x i64>* %b
677 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
678 %3 = ashr <2 x i64> %1, %2
679 ; CHECK-DAG: sra.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
680 store <2 x i64> %3, <2 x i64>* %c
681 ; CHECK-DAG: st.d [[R3]], 0($4)
682
683 ret void
684 ; CHECK: .size sra_v2i64
685}
686
Daniel Sanderscba19222013-09-24 10:28:18 +0000[diff] [blame]687define void @sra_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
688 ; CHECK: sra_v16i8_i:
689
690 %1 = load <16 x i8>* %a
691 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
692 %2 = ashr <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
693 ; CHECK-DAG: srai.b [[R4:\$w[0-9]+]], [[R1]], 1
694 store <16 x i8> %2, <16 x i8>* %c
695 ; CHECK-DAG: st.b [[R4]], 0($4)
696
697 ret void
698 ; CHECK: .size sra_v16i8_i
699}
700
701define void @sra_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
702 ; CHECK: sra_v8i16_i:
703
704 %1 = load <8 x i16>* %a
705 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
706 %2 = ashr <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
707 ; CHECK-DAG: srai.h [[R4:\$w[0-9]+]], [[R1]], 1
708 store <8 x i16> %2, <8 x i16>* %c
709 ; CHECK-DAG: st.h [[R4]], 0($4)
710
711 ret void
712 ; CHECK: .size sra_v8i16_i
713}
714
715define void @sra_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
716 ; CHECK: sra_v4i32_i:
717
718 %1 = load <4 x i32>* %a
719 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
720 %2 = ashr <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
721 ; CHECK-DAG: srai.w [[R4:\$w[0-9]+]], [[R1]], 1
722 store <4 x i32> %2, <4 x i32>* %c
723 ; CHECK-DAG: st.w [[R4]], 0($4)
724
725 ret void
726 ; CHECK: .size sra_v4i32_i
727}
728
729define void @sra_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
730 ; CHECK: sra_v2i64_i:
731
732 %1 = load <2 x i64>* %a
733 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
734 %2 = ashr <2 x i64> %1, <i64 1, i64 1>
735 ; CHECK-DAG: srai.d [[R4:\$w[0-9]+]], [[R1]], 1
736 store <2 x i64> %2, <2 x i64>* %c
737 ; CHECK-DAG: st.d [[R4]], 0($4)
738
739 ret void
740 ; CHECK: .size sra_v2i64_i
741}
742
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame]743define void @srl_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
744 ; CHECK: srl_v16i8:
745
746 %1 = load <16 x i8>* %a
747 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
748 %2 = load <16 x i8>* %b
749 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
750 %3 = lshr <16 x i8> %1, %2
751 ; CHECK-DAG: srl.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
752 store <16 x i8> %3, <16 x i8>* %c
753 ; CHECK-DAG: st.b [[R3]], 0($4)
754
755 ret void
756 ; CHECK: .size srl_v16i8
757}
758
759define void @srl_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
760 ; CHECK: srl_v8i16:
761
762 %1 = load <8 x i16>* %a
763 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
764 %2 = load <8 x i16>* %b
765 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
766 %3 = lshr <8 x i16> %1, %2
767 ; CHECK-DAG: srl.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
768 store <8 x i16> %3, <8 x i16>* %c
769 ; CHECK-DAG: st.h [[R3]], 0($4)
770
771 ret void
772 ; CHECK: .size srl_v8i16
773}
774
775define void @srl_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
776 ; CHECK: srl_v4i32:
777
778 %1 = load <4 x i32>* %a
779 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
780 %2 = load <4 x i32>* %b
781 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
782 %3 = lshr <4 x i32> %1, %2
783 ; CHECK-DAG: srl.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
784 store <4 x i32> %3, <4 x i32>* %c
785 ; CHECK-DAG: st.w [[R3]], 0($4)
786
787 ret void
788 ; CHECK: .size srl_v4i32
789}
790
791define void @srl_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
792 ; CHECK: srl_v2i64:
793
794 %1 = load <2 x i64>* %a
795 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
796 %2 = load <2 x i64>* %b
797 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
798 %3 = lshr <2 x i64> %1, %2
799 ; CHECK-DAG: srl.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
800 store <2 x i64> %3, <2 x i64>* %c
801 ; CHECK-DAG: st.d [[R3]], 0($4)
802
803 ret void
804 ; CHECK: .size srl_v2i64
805}
806
Daniel Sanderscba19222013-09-24 10:28:18 +0000[diff] [blame]807define void @srl_v16i8_i(<16 x i8>* %c, <16 x i8>* %a) nounwind {
808 ; CHECK: srl_v16i8_i:
809
810 %1 = load <16 x i8>* %a
811 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
812 %2 = lshr <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
813 ; CHECK-DAG: srli.b [[R4:\$w[0-9]+]], [[R1]], 1
814 store <16 x i8> %2, <16 x i8>* %c
815 ; CHECK-DAG: st.b [[R4]], 0($4)
816
817 ret void
818 ; CHECK: .size srl_v16i8_i
819}
820
821define void @srl_v8i16_i(<8 x i16>* %c, <8 x i16>* %a) nounwind {
822 ; CHECK: srl_v8i16_i:
823
824 %1 = load <8 x i16>* %a
825 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
826 %2 = lshr <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
827 ; CHECK-DAG: srli.h [[R4:\$w[0-9]+]], [[R1]], 1
828 store <8 x i16> %2, <8 x i16>* %c
829 ; CHECK-DAG: st.h [[R4]], 0($4)
830
831 ret void
832 ; CHECK: .size srl_v8i16_i
833}
834
835define void @srl_v4i32_i(<4 x i32>* %c, <4 x i32>* %a) nounwind {
836 ; CHECK: srl_v4i32_i:
837
838 %1 = load <4 x i32>* %a
839 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
840 %2 = lshr <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
841 ; CHECK-DAG: srli.w [[R4:\$w[0-9]+]], [[R1]], 1
842 store <4 x i32> %2, <4 x i32>* %c
843 ; CHECK-DAG: st.w [[R4]], 0($4)
844
845 ret void
846 ; CHECK: .size srl_v4i32_i
847}
848
849define void @srl_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
850 ; CHECK: srl_v2i64_i:
851
852 %1 = load <2 x i64>* %a
853 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
854 %2 = lshr <2 x i64> %1, <i64 1, i64 1>
855 ; CHECK-DAG: srli.d [[R4:\$w[0-9]+]], [[R1]], 1
856 store <2 x i64> %2, <2 x i64>* %c
857 ; CHECK-DAG: st.d [[R4]], 0($4)
858
859 ret void
860 ; CHECK: .size srl_v2i64_i
861}
862
Daniel Sanders766cb692013-09-23 13:40:21 +0000[diff] [blame]863define void @ctpop_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
864 ; CHECK: ctpop_v16i8:
865
866 %1 = load <16 x i8>* %a
867 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
868 %2 = tail call <16 x i8> @llvm.ctpop.v16i8 (<16 x i8> %1)
869 ; CHECK-DAG: pcnt.b [[R3:\$w[0-9]+]], [[R1]]
870 store <16 x i8> %2, <16 x i8>* %c
871 ; CHECK-DAG: st.b [[R3]], 0($4)
872
873 ret void
874 ; CHECK: .size ctpop_v16i8
875}
876
877define void @ctpop_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
878 ; CHECK: ctpop_v8i16:
879
880 %1 = load <8 x i16>* %a
881 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
882 %2 = tail call <8 x i16> @llvm.ctpop.v8i16 (<8 x i16> %1)
883 ; CHECK-DAG: pcnt.h [[R3:\$w[0-9]+]], [[R1]]
884 store <8 x i16> %2, <8 x i16>* %c
885 ; CHECK-DAG: st.h [[R3]], 0($4)
886
887 ret void
888 ; CHECK: .size ctpop_v8i16
889}
890
891define void @ctpop_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
892 ; CHECK: ctpop_v4i32:
893
894 %1 = load <4 x i32>* %a
895 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
896 %2 = tail call <4 x i32> @llvm.ctpop.v4i32 (<4 x i32> %1)
897 ; CHECK-DAG: pcnt.w [[R3:\$w[0-9]+]], [[R1]]
898 store <4 x i32> %2, <4 x i32>* %c
899 ; CHECK-DAG: st.w [[R3]], 0($4)
900
901 ret void
902 ; CHECK: .size ctpop_v4i32
903}
904
905define void @ctpop_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
906 ; CHECK: ctpop_v2i64:
907
908 %1 = load <2 x i64>* %a
909 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
910 %2 = tail call <2 x i64> @llvm.ctpop.v2i64 (<2 x i64> %1)
911 ; CHECK-DAG: pcnt.d [[R3:\$w[0-9]+]], [[R1]]
912 store <2 x i64> %2, <2 x i64>* %c
913 ; CHECK-DAG: st.d [[R3]], 0($4)
914
915 ret void
916 ; CHECK: .size ctpop_v2i64
917}
918
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame]919define void @ctlz_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
920 ; CHECK: ctlz_v16i8:
921
922 %1 = load <16 x i8>* %a
923 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
924 %2 = tail call <16 x i8> @llvm.ctlz.v16i8 (<16 x i8> %1)
925 ; CHECK-DAG: nlzc.b [[R3:\$w[0-9]+]], [[R1]]
926 store <16 x i8> %2, <16 x i8>* %c
927 ; CHECK-DAG: st.b [[R3]], 0($4)
928
929 ret void
930 ; CHECK: .size ctlz_v16i8
931}
932
933define void @ctlz_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
934 ; CHECK: ctlz_v8i16:
935
936 %1 = load <8 x i16>* %a
937 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
938 %2 = tail call <8 x i16> @llvm.ctlz.v8i16 (<8 x i16> %1)
939 ; CHECK-DAG: nlzc.h [[R3:\$w[0-9]+]], [[R1]]
940 store <8 x i16> %2, <8 x i16>* %c
941 ; CHECK-DAG: st.h [[R3]], 0($4)
942
943 ret void
944 ; CHECK: .size ctlz_v8i16
945}
946
947define void @ctlz_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
948 ; CHECK: ctlz_v4i32:
949
950 %1 = load <4 x i32>* %a
951 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
952 %2 = tail call <4 x i32> @llvm.ctlz.v4i32 (<4 x i32> %1)
953 ; CHECK-DAG: nlzc.w [[R3:\$w[0-9]+]], [[R1]]
954 store <4 x i32> %2, <4 x i32>* %c
955 ; CHECK-DAG: st.w [[R3]], 0($4)
956
957 ret void
958 ; CHECK: .size ctlz_v4i32
959}
960
961define void @ctlz_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
962 ; CHECK: ctlz_v2i64:
963
964 %1 = load <2 x i64>* %a
965 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
966 %2 = tail call <2 x i64> @llvm.ctlz.v2i64 (<2 x i64> %1)
967 ; CHECK-DAG: nlzc.d [[R3:\$w[0-9]+]], [[R1]]
968 store <2 x i64> %2, <2 x i64>* %c
969 ; CHECK-DAG: st.d [[R3]], 0($4)
970
971 ret void
972 ; CHECK: .size ctlz_v2i64
973}
974
Daniel Sanders766cb692013-09-23 13:40:21 +0000[diff] [blame]975declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %val)
976declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %val)
977declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %val)
978declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val)
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame]979declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %val)
980declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %val)
981declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val)
982declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %val)