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gerrit-public.fairphone.software / toolchain / llvm-project / 1b6dacbb86d9c426bd3cb009a446e7da441fd97c / . / llvm / test / CodeGen / Thumb2 / thumb2-and.ll
blob: 1984b3ffb356ba1ef8239cb557135db0c91944d0 [file] [log] [blame]
Saleem Abdulrasool905b6d192014-04-03 23:47:24 +0000[diff] [blame]1; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
David Goodwin3aaa7512009-06-26 22:37:07 +0000[diff] [blame]2
3define i32 @f1(i32 %a, i32 %b) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]4; CHECK-LABEL: f1:
Evan Cheng475f8a42009-08-10 23:56:04 +0000[diff] [blame]5; CHECK: ands r0, r1
David Goodwin3aaa7512009-06-26 22:37:07 +0000[diff] [blame]6 %tmp = and i32 %a, %b
7 ret i32 %tmp
8}
David Goodwin17512662009-06-30 01:02:20 +0000[diff] [blame]9
10define i32 @f2(i32 %a, i32 %b) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]11; CHECK-LABEL: f2:
Evan Cheng475f8a42009-08-10 23:56:04 +0000[diff] [blame]12; CHECK: and.w r0, r0, r1, lsl #5
David Goodwin17512662009-06-30 01:02:20 +0000[diff] [blame]13 %tmp = shl i32 %b, 5
14 %tmp1 = and i32 %a, %tmp
15 ret i32 %tmp1
16}
17
18define i32 @f3(i32 %a, i32 %b) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]19; CHECK-LABEL: f3:
Evan Cheng475f8a42009-08-10 23:56:04 +0000[diff] [blame]20; CHECK: and.w r0, r0, r1, lsr #6
David Goodwin17512662009-06-30 01:02:20 +0000[diff] [blame]21 %tmp = lshr i32 %b, 6
22 %tmp1 = and i32 %a, %tmp
23 ret i32 %tmp1
24}
25
26define i32 @f4(i32 %a, i32 %b) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]27; CHECK-LABEL: f4:
Evan Cheng475f8a42009-08-10 23:56:04 +0000[diff] [blame]28; CHECK: and.w r0, r0, r1, asr #7
David Goodwin17512662009-06-30 01:02:20 +0000[diff] [blame]29 %tmp = ashr i32 %b, 7
30 %tmp1 = and i32 %a, %tmp
31 ret i32 %tmp1
32}
33
34define i32 @f5(i32 %a, i32 %b) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]35; CHECK-LABEL: f5:
Evan Cheng475f8a42009-08-10 23:56:04 +0000[diff] [blame]36; CHECK: and.w r0, r0, r0, ror #8
David Goodwin17512662009-06-30 01:02:20 +0000[diff] [blame]37 %l8 = shl i32 %a, 24
38 %r8 = lshr i32 %a, 8
39 %tmp = or i32 %l8, %r8
40 %tmp1 = and i32 %a, %tmp
41 ret i32 %tmp1
42}