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gerrit-public.fairphone.software / toolchain / llvm-project / 25793a3f2295397583aa9243d0a9d8676dd0c8a8 / . / llvm / lib / Target / R600 / SIISelLowering.h
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Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief SI DAG Lowering interface definition
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SIISELLOWERING_H
16#define SIISELLOWERING_H
17
18#include "AMDGPUISelLowering.h"
19#include "SIInstrInfo.h"
20
21namespace llvm {
22
23class SITargetLowering : public AMDGPUTargetLowering {
Tom Stellardaf775432013-10-23 00:44:32 +0000[diff] [blame]24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
Tom Stellard94593ee2013-06-03 17:40:18 +0000[diff] [blame]25 SDValue Chain, unsigned Offset) const;
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27 SelectionDAG &DAG) const;
Tom Stellard81d871d2013-11-13 23:36:50 +0000[diff] [blame]28 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
Tom Stellard0ec134f2014-02-04 17:18:40 +0000[diff] [blame]29 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]30 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
Tom Stellard046039e2013-06-03 17:40:03 +0000[diff] [blame]31 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
Tom Stellard81d871d2013-11-13 23:36:50 +0000[diff] [blame]32 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
Tom Stellard98f675a2013-08-01 15:23:26 +0000[diff] [blame]33 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
Matt Arsenaultfb826fa2013-11-18 20:09:47 +0000[diff] [blame]34 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]35 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]36
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]37 SDValue ResourceDescriptorToi128(SDValue Op, SelectionDAG &DAG) const;
Christian Konigf82901a2013-02-26 17:52:23 +0000[diff] [blame]38 bool foldImm(SDValue &Operand, int32_t &Immediate,
39 bool &ScalarSlotUsed) const;
Tom Stellard4c0ffcc2013-08-06 23:08:18 +0000[diff] [blame]40 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
41 const SDValue &Op) const;
Tom Stellardb35efba2013-05-20 15:02:01 +0000[diff] [blame]42 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
43 unsigned RegClass) const;
Matt Arsenault758659232013-05-18 00:21:46 +0000[diff] [blame]44 void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
Christian Konigf82901a2013-02-26 17:52:23 +0000[diff] [blame]45 unsigned RegClass, bool &ScalarSlotUsed) const;
46
Christian Konig8e06e2a2013-04-10 08:39:08 +0000[diff] [blame]47 SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
48 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
Tom Stellard0518ff82013-06-03 17:39:58 +0000[diff] [blame]49 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
Christian Konig8e06e2a2013-04-10 08:39:08 +0000[diff] [blame]50
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]51public:
52 SITargetLowering(TargetMachine &tm);
Matt Arsenault25793a32014-02-05 23:15:53 +0000[diff] [blame^]53 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS, bool *IsFast) const;
Tom Stellardd86003e2013-08-14 23:25:00 +0000[diff] [blame]54 virtual bool shouldSplitVectorElementType(EVT VT) const;
Christian Konig2c8f6d52013-03-07 09:03:52 +0000[diff] [blame]55
56 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
57 bool isVarArg,
58 const SmallVectorImpl<ISD::InputArg> &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]59 SDLoc DL, SelectionDAG &DAG,
Christian Konig2c8f6d52013-03-07 09:03:52 +0000[diff] [blame]60 SmallVectorImpl<SDValue> &InVals) const;
61
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]62 virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
63 MachineBasicBlock * BB) const;
Matt Arsenault758659232013-05-18 00:21:46 +0000[diff] [blame]64 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
Christian Konig082a14a2013-03-18 11:34:05 +0000[diff] [blame]65 virtual MVT getScalarShiftAmountTy(EVT VT) const;
Niels Ole Salscheiderd3a039f2013-08-10 10:38:54 +0000[diff] [blame]66 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]67 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
68 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
Christian Konigd910b7d2013-02-26 17:52:16 +0000[diff] [blame]69 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const;
Christian Konig8b1ed282013-04-10 08:39:16 +0000[diff] [blame]70 virtual void AdjustInstrPostInstrSelection(MachineInstr *MI,
71 SDNode *Node) const;
Christian Konigf82901a2013-02-26 17:52:23 +0000[diff] [blame]72
73 int32_t analyzeImmediate(const SDNode *N) const;
Tom Stellard94593ee2013-06-03 17:40:18 +0000[diff] [blame]74 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
75 unsigned Reg, EVT VT) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]76};
77
78} // End namespace llvm
79
80#endif //SIISELLOWERING_H